The proceedings contain 30 papers. The topics discussed include: reliability-aware multi-vth domain digital design assessment;replication-based deterministic testing of 2-dimensional arrays with highly interrelated ce...
ISBN:
(纸本)9781538657546
The proceedings contain 30 papers. The topics discussed include: reliability-aware multi-vth domain digital design assessment;replication-based deterministic testing of 2-dimensional arrays with highly interrelated cells;contribution to automated generating of system power-management specification;a rare event based yield estimation methodology for analog circuits;two-stage bulk-driven variable gain amplifier for low-voltage applications;heuristic for page-based incremental reprogramming of wireless sensor nodes;tuning stochastic space compaction to faster-than-at-speed test;constraint-based pattern retargeting for reducing localized power activity during testing;and an integrated phase shifting frequency synthesizer for active electronically scanned arrays.
The proceedings contain 28 papers. The topics discussed include: evaluating the reliability of integer multipliers with respect to permanent faults;a ML-based approach for finding the product definition space of micro...
ISBN:
(纸本)9798350359343
The proceedings contain 28 papers. The topics discussed include: evaluating the reliability of integer multipliers with respect to permanent faults;a ML-based approach for finding the product definition space of microelectronic power switches;a comparison of logic extraction methods in hardware-translated neural networks;performance and error tolerance of stochastic computing-based digital filter design;ABACUS: ASIP-based Avro schema-customizable parser acceleration on FPGAs;fault-simulation-based flip-flop classification for reverse engineering;choose your path: control of ring oscillators EMFI susceptibility through FPGA P&R constraints;and a low-noise high-voltage rail-to-rail operational amplifier with gain stabilization and slew-rate enhancement.
The proceedings contain 35 papers. The topics discussed include: evaluating the hardware performance counters of an Xtensa virtual prototype;data-driven test generation for black-box systems from learned decision tree...
ISBN:
(纸本)9798350332773
The proceedings contain 35 papers. The topics discussed include: evaluating the hardware performance counters of an Xtensa virtual prototype;data-driven test generation for black-box systems from learned decision tree models;reducing output response aliasing using Boolean optimization techniques;prediction of inference energy on CNN accelerators supporting approximate circuits;supporting analog design for reliability by efficient provision of reliability information to designers;efficient binary decision diagram manipulation by reducing the number of intermediate nodes;a low-cost residue-based scheme for error-resiliency of RNN accelerators;counterfeit chip detection using scattering parameter analysis;quality assessment of logic locking mechanisms using pseudo-Boolean optimization techniques;a digital delay model supporting large adversarial delay variations;and a configurable mixed-precision convolution processing unit generator in chisel.
The proceedings contain 30 papers. The topics discussed include: towards polynomial formal verification of complex arithmetic circuits;dependability of alternative computing paradigms for machine learning: hype or hop...
ISBN:
(纸本)9781665494311
The proceedings contain 30 papers. The topics discussed include: towards polynomial formal verification of complex arithmetic circuits;dependability of alternative computing paradigms for machine learning: hype or hope?;virtual prototype driven design, implementation and evaluation of RISC-V instruction set extensions;processor extensions for hardware instruction replay against fault injection attacks;a design space exploration framework for memristor-based crossbar architecture;hexapod robotic system for indoor neutron and gamma radiation mapping and inspection;exploiting PUF variation to detect fault injection attacks;versatile hardware framework for elliptic curve cryptography;functional verification of arithmetic circuits: survey of formal methods;on SAT-based model checking of speed-independent circuits;and synaptic control for hardware implementation of spike timing dependent plasticity.
Binary comparator networks have already been used in quasi delay-insensitive (QDI) circuit design for the construction of completion detectors. This paper demonstrates how they can also be utilized to implement a wide...
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ISBN:
(纸本)9798350359343
Binary comparator networks have already been used in quasi delay-insensitive (QDI) circuit design for the construction of completion detectors. This paper demonstrates how they can also be utilized to implement a wide range of Boolean functions for combinational QDI logic blocks. designing combinational logic for QDI circuits poses several challenges because data must be processed in an encoded form (usually dual-rail) and it must be ensured that the resulting circuits do not contain hazards or orphans. These design constraints impose a considerable hardware overhead on the resulting circuits. Hence, over the years numerous design and optimization strategies have been proposed. We show that our comparator-network-based construction approach yields promising results for certain types of functions compared to other common QDI design styles.
Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such...
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ISBN:
(纸本)9798350359343
Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.
This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage (V-th) in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendor...
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ISBN:
(纸本)9798350359343
This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage (V-th) in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). The results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 mu m or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.
Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are ...
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ISBN:
(纸本)9798350359343
Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are combinational. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. The first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. The response to activation values that have not occurred in the training set remains unspecified. The other approach uses a complete set of activation values at the input of the examined part. We measured accuracy, the influence of logic minimization, and their impact on the final synthesized circuit on dense neural networks in different stages of low-magnitude pruning on the MNIST and JSC datasets. The results show that the first method can be used for functions with fan-in below 10-12 while not working against generalization. We also document the quantitative changes in quantized networks.
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