In hardware video encoders, the quantization and dequantization modules can consume a significant amount of hardware resources. This paper presents optimization methods for FPGA architectures of the modules. The metho...
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ISBN:
(纸本)9781479945580
In hardware video encoders, the quantization and dequantization modules can consume a significant amount of hardware resources. This paper presents optimization methods for FPGA architectures of the modules. The methods allow a better utilization of resources available in DSP units and the reduction of general-purpose logic elements. Different versions of architectures are developed for FPGA Altera Arria II devices. Implementation results show that the multiple reduction of general-purpose logic is achieved. Moreover, the utilization of registers embedded in DSP allows the doubled clock frequency.
This paper deals with design of Physical Unclonable Functions (PUFs) based on FPGA. The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. The...
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ISBN:
(纸本)9781479967803
This paper deals with design of Physical Unclonable Functions (PUFs) based on FPGA. The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. Therefore, a proposal of a ring oscillator (RO) based PUF producing more output bits from one RO pair is presented. 24 Digilent Basys 2 FPGA boards were tested and statistically evaluated indicating suitability of the proposed design for device identification.
This paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. The circuit is described and a model is provided to estimate data-rate ...
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ISBN:
(纸本)1424401844
This paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. The circuit is described and a model is provided to estimate data-rate and expected quality of the generated bit sequence. Since the noise source is quasi-stateless, its deterministic evolution does not present complex patterns and therefore a lack of entropy and faults can be detected on-line.
Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is not met in terms of functionality in order to obtain some improvements in power consumption, performan...
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ISBN:
(纸本)9781479945580
Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is not met in terms of functionality in order to obtain some improvements in power consumption, performance or area, in comparison with fully functional circuits. In this paper, we propose to design approximate circuits using evolutionary design techniques. In particular, different error metrics are utilized to assess the circuit functionality. The proposed method begins with a fully functional circuit which is then intentionally degraded by Cartesian genetic programming (CGP) to obtain a circuit with a predefined error. In the second phase, CGP is used to minimize the number of gates or another error criterion. The effect of various error metrics on the search performance, area and power consumption is evaluated in the task of multiplier design.
Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this pap...
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ISBN:
(纸本)9781467361361;9781467361354
Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this paper, an efficient approach to automate speedpath debugging is presented. The approach relies on converting the timing behavior of a circuit and its corresponding timing variations into functional domain. Afterwards, a SAT-based debug engine is utilized to extract potential failing speedpaths. The experimental results on ISCAS' 85 and ISCAS'89 benchmark suites show that our approach achieves a 63% decrease in the size of model resulting in 54% decrease in the debugging time compared to previous work while having a high diagnosis accuracy.
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18 mu m CMOS. We have designed the self-timed processor using the same RTL as the synchronous ...
ISBN:
(纸本)9781424433391
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18 mu m CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.
This article describes optimization of excitation signal for purpose of fault diagnosis. The goal is to enhance efficiency of faults detection in analog electroniccircuits. The method has been verified on cases with ...
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ISBN:
(纸本)9781424422760
This article describes optimization of excitation signal for purpose of fault diagnosis. The goal is to enhance efficiency of faults detection in analog electroniccircuits. The method has been verified on cases with single hard (catastrophic) and soft (parametric) faults. Further enhancement of fault detection efficiency has been achieved with additional feature extraction by means of wavelet transform. Obtained results have been compared with diagnosis using step function excitation and diagnosis without feature extraction.
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The imple...
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ISBN:
(纸本)9781479967803
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The implementations include both multiplicative inverse and division. The proposed hardware implementations are designed with high computation speed and throughput. They are oriented for high computation demanding applications with multiple division computations in short sequences.
An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers ...
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ISBN:
(纸本)9781424433391
An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers a conversion gain of 22dB at a clock frequency of 1.5GHz for GALILEO/GPS applications. The design is capable of operating at up to 7GHz with only 3dB gain decrease. The simulated noise figure is 27dB with a power consumption of 730 mu W. Simulations at a supply voltage of 0.9V instead of 1.2V show a gain decrease of only 3dB while the noise figure increases by 2dB.
The paper describes a reconfigurable polymorphic chip REPOMO32, experiments carried out with this chip and provides report on important experiences with regard to practical applications of digital polymorphic circuits...
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ISBN:
(纸本)9781424466139
The paper describes a reconfigurable polymorphic chip REPOMO32, experiments carried out with this chip and provides report on important experiences with regard to practical applications of digital polymorphic circuits sensitive to the power supply voltage (V-dd). REPOMO32 contains array of 32 configurable logic elements which can perform polymorphic NAND/NOR function controlled by the level of the V-dd. Moreover, it can be declared as the first fabricated chip of this kind which basically allows the user to design more complex circuits than only a few gates.
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