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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"
4789 条 记 录,以下是91-100 订阅
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FPGA Architectures of the Quantization and the Dequantization for Video Encoders  17
FPGA Architectures of the Quantization and the Dequantizatio...
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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Pastuszak, Grzegorz Warsaw Univ Technol Inst Radioelect PL-00665 Warsaw Poland
In hardware video encoders, the quantization and dequantization modules can consume a significant amount of hardware resources. This paper presents optimization methods for FPGA architectures of the modules. The metho... 详细信息
来源: 评论
A design of ring oscillator based PUF on FPGA  18
A design of ring oscillator based PUF on FPGA
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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Kodytek, Filip Lorenez, Robert Czech Tech Univ Dept Comp Syst Thakurova 9 Prague Czech Republic
This paper deals with design of Physical Unclonable Functions (PUFs) based on FPGA. The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. The... 详细信息
来源: 评论
A leakage-based random bit generator with on-line fault detection
A leakage-based random bit generator with on-line fault dete...
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9th ieee Workshop on design and diagnostics of electronic circuits and systems
作者: Bucci, Marco Luzzi, Raimondo Infineon Technologies AG Germany
This paper presents a new, patent pending, random bit generator whose noise source exploits the leakage current in a reverse biased p-n junction. The circuit is described and a model is provided to estimate data-rate ... 详细信息
来源: 评论
Evolutionary design of Approximate Multipliers Under Different Error Metrics  17
Evolutionary Design of Approximate Multipliers Under Differe...
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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Vasicek, Zdenek Sekanina, Lukas Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat CS-61090 Brno Czech Republic
Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is not met in terms of functionality in order to obtain some improvements in power consumption, performan... 详细信息
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Efficient Automated Speedpath Debugging
Efficient Automated Speedpath Debugging
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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Dehbashi, Mehdi Fey, Goerschwin Univ Bremen Inst Comp Sci D-28359 Bremen Germany
Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this pap... 详细信息
来源: 评论
Measurement of Power Supply Noise Tolerance of Self-timed Processor
Measurement of Power Supply Noise Tolerance of Self-timed Pr...
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ieee symposium on design and diagnostics of electronic circuits and systems
作者: Asada, Kunihiro Sogabe, Taku Nakura, Toru Ikeda, Makoto Univ Tokyo Dept Elect Engn Bunkyo Ku 7-3-1 Hongo Tokyo 1138656 Japan VLSI Design Educ Ctr Bunkyo Ku Tokyo 1138656 Japan
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18 mu m CMOS. We have designed the self-timed processor using the same RTL as the synchronous ...
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Excitation optimization in fault diagnosis of analog electronic circuits
Excitation optimization in fault diagnosis of analog electro...
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11th ieee International Workshop on design and diagnostics of electronic circuits and systems
作者: Chruszczyk, L. Rutkowski, J. Silesian Tech Univ Inst Elect Gliwice Poland
This article describes optimization of excitation signal for purpose of fault diagnosis. The goal is to enhance efficiency of faults detection in analog electronic circuits. The method has been verified on cases with ... 详细信息
来源: 评论
High throughput floating-point dividers implemented in FPGA  18
High throughput floating-point dividers implemented in FPGA
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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Malik, Peter Slovak Acad Sci Inst Informat Dubravska Cesta 9 Bratislava 84507 Slovakia
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The imple... 详细信息
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Low-Voltage Low-Power Double Bulk Mixer for Direct Conversion Receiver in 65nm CMOS
Low-Voltage Low-Power Double Bulk Mixer for Direct Conversio...
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ieee symposium on design and diagnostics of electronic circuits and systems
作者: Schweiger, Kurt Uhrmann, Heimo Zimmermann, Horst Vienna Univ Technol Inst Elect Measurements & Circuit Design A-1040 Vienna Austria
An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers ... 详细信息
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On Analysis of Fabricated Polymorphic circuits
On Analysis of Fabricated Polymorphic Circuits
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13th ieee symposium on design and diagnostics of electronic circuits and systems
作者: Simek, Vaclav Ruzicka, Richard Sekanina, Lukas Brno Univ Technol Fac Informat Technol Brno Czech Republic
The paper describes a reconfigurable polymorphic chip REPOMO32, experiments carried out with this chip and provides report on important experiences with regard to practical applications of digital polymorphic circuits... 详细信息
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