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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Using Model Checker to Analyze and Test Digital circuits with Regard to Delay Faults 24

Using Model Checker to Analyze and Test Digital Circuits wit...

引用

24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Strnadel, Josef Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781665435956

Narrow timing margins in modern digital circuits result in delay defects that are difficult to detect. The probability that such a defect occurs increases with factors such as shrinking feature sizes, increasing process variations, operating frequencies, and aging/stress of the circuits. Traditionally, timing is considered in connection with the logic design, physical design and layout, and delay testing phases of the circuit development process and builds on principles of delay characterization, fault models and timing analysis. This paper presents a model checking approach aiming to facilitate the solutions of problems with regard to analyzing consequences and testing of delay faults. Our approach expects that a circuit is modeled as a network of stochastic hybrid timed automata capable to describe the circuit both in the logical and temporal domains, including facts such as uncertainty and variations. In our approach, we gather attributes and formalize expected properties of a circuit and transform the circuit into our model. Then, we use a statistical model checker to check the properties and to produce a counter-example for each property being violated. Further, we transform the counter-examples into test cases and finally, into a delay test able to check whether the timing requirements are met.

关键词： digital circuit timing delay fault timed automaton model checking counter-example test case test

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A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis 24

A Parameterizable Chisel Generator of Numerically Controlled...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Damnjanovic, Vukan D. Petrovic, Marija L. Milovanovic, Vladimir M. Univ Kragujevac Fac Engn Sestre Janjic 6 Kragujevac Serbia NOVELIC Veljka Dugosevica 54 Belgrade Serbia

ISBN: (纸本)9781665435956

Numerically controlled oscillators (NCOs) as part of direct digital synthesizers (DDS) are important components in many digital communication subsystems, such as various digital modulation and demodulation schemes, up and down converters, radar, sonar and laser appliances, etc. The vast number of their beneficial characteristics is what makes NCOs so widely used. Taking this into account, a parameterizable generator of numerically controlled oscillators is implemented using Chisel hardware design language. The proposed generator provides a broad range of parameter configurations, such as input and output data types and widths, the number of different output samples, optional use of spur-reducing techniques or different input interfaces, just to name a few. Numerous generated instances have been tested in software simulations and mapped and tested onto a commercial FPGA platform. Obtained results proved that a generator of this kind can legitimately be compared with custom designed NCO modules, both in terms of performance and resource utilization.

关键词： Numerically controlled oscillator direct digital synthesizer Chisel hardware design language design generator

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Fusing EO and LiDAR for SAR Image Translation with Multi-Modal Generative Adversarial Networks

Fusing EO and LiDAR for SAR Image Translation with Multi-Mod...

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2024 ieee International symposium on circuits and systems, ISCAS 2024

作者： Zhu, Jiang Qing, Yuanyuan Lin, Zhiping Wen, Bihan Nanyang Technological University School of Electrical And Electronic Engineering Singapore

ISBN: (纸本)9798350330991

To generate high-quality Synthetic Aperture Radar (SAR) images, the translation of Electro-optical (EO) to SAR images has been studied in recent years. However, these methods cannot make use of other modal information, such as Light Detection and Ranging (LiDAR), to enhance their performance, due to the absence of well-registered multi-modal remote sensing data. Therefore, in this paper, we first construct an organized high-resolution real-world benchmark dataset, which comprises 479 registered multi-modal images. We then explore how to adapt the state-of-the-art method, named the query-selected attention model (QS-Attn), to make it more suitable for integrating EO and LiDAR images into real SAR image translation. Extensive experiments have been conducted to evaluate our proposed method and compare it with state-of-the-art methods. The experimental results validate the superiority and effectiveness of our approach. © 2024 ieee.

关键词： Synthetic aperture radar

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QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware design on RTL

QTFlow: Quantitative Timing-Sensitive Information Flow for S...

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International VLSI symposium on Technology, systems and Applications (VLSI)

作者： Reimann, Lennart M. Prashar, Anshul Ghinami, Chiara Pelke, Rebecca Sisejkovic, Dominik Merchant, Farhad Leupers, Rainer Rhein Westfal TH Aachen Aachen Germany Robert Bosch GmbH Corp Res Gerlingen Germany Newcastle Univ Newcastle Upon Tyne Tyne & Wear England

ISBN: (纸本)9798350360356;9798350360349

In contemporary electronic design Automation (EDA) tools, security often takes a backseat to the primary goals of power, performance, and area optimization. Commonly, the security analysis is conducted by hand, leading to vulnerabilities in the design remaining unnoticed. Security-aware EDA tools assist the designer in the identification and removal of security threats while keeping performance and area in mind. Cutting-edge methods employ information flow analysis to identify inadvertent information leaks in design structures. Current information leakage detection methods use quantitative information flow analysis to quantify the leaks. However, handling sequential circuits poses challenges for state-of-the-art techniques due to their time-agnostic nature, overlooking timing channels, and introducing false positives. To address this, we introduce QTFlow, a timing-sensitive framework for quantifying hardware information leakages during the design phase. Illustrating its effectiveness on open-source benchmarks, QTFlow autonomously identifies timing channels and diminishes all false positives arising from time-agnostic analysis when contrasted with current state-of-the-art techniques.

关键词： quantitative information flow confidentiality hardware security timing channels

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The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies

The Impact of Well-Edge Proximity Effect on PMOS Threshold V...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Marika Grochowska Witold A. Pleskacz Cadence Design Systems Warsaw Poland Warsaw University of Technology Institute of Microelectronics & Optoelectronics Warsaw Poland

This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage $(V_{th})$ in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). The results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 μm or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.

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design Exploration of CMOS Building Blocks for Time-Based-Controlled DC-DC Converters Using Open-Source PDK and Tools 16

Design Exploration of CMOS Building Blocks for Time-Based-Co...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Marin, Jorge Martinez, Andres Nuncz, Andrea Rojas, Christian A. Universidad Tecnica Federico Santa Maria Department of Electronic Eng. Valparaiso Chile Advanced Center of Electrical and Electronics Engineering Universidad Técnica Federico Santa María Chile

ISBN: (纸本)9798331522124

This paper presents the design and system integration of low-power analog and digital building blocks intended for DC-DC buck converters used in IoT applications by using time-based control techniques. Each building block has been independently simulated to extract the relevant parameters for the full system. Simulation results in steady-state behaviour of the DC-DC buck converter and its system efficiency using open-source CAD tools are provided to demonstrate the effective operation of the time-based control. The maximum simulated efficiency yields 85.8 % for a conversion from 3.3 V to 1.8 V and a 270 mA load current, with a switching frequency of 1.9 MHz. The blocks have been implemented in the Skywater open-source 130-nm CMOS process, with an estimated total area of 0.27 mm2, from which the controller area represents only 4.4%. © 2025 ieee.

关键词： CMOS integrated circuits

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Synthesis of approximate circuits for LUT-based FPGAs 24

Synthesis of approximate circuits for LUT-based FPGAs

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Vasicek, Zdenek Brno Univ Technol Fac Informat Technol IT4Innovat Ctr Excellence Brno Czech Republic

ISBN: (纸本)9781665435956

Approximate computing is an emerging paradigm that trades the accuracy of computation to achieve gain in terms of design area, critical path delay and/or power consumption. There is a rich body of literature showing that the approximate hardware components serving as basic building blocks for energy-efficient implementation of complex systems offer a remarkable gain in efficiency and/or performance in exchange for small losses in output quality. However, recent studies revealed that the approximate components optimized mainly for ASICs offer asymmetric gain when used in FPGAs. In this work, we present an iterative design method for automated synthesis of elementary approximate components natively optimized for usage in LUT-based FPGAs. The method takes into account the number of LUTs and LUT-level propagation delay instead of the number of gates and logic levels typically considered in other works. Using this method, we synthesized various approximate adders (up to 64-bit) and multipliers (8-bit and 16-bit). Compared to the current state-of-the-art, our designs achieve better trade-off when considered the worst case absolute error, number of LUTs and propagation delay. The discovered approximate adders and multipliers are available online in the form of Verilog netlists consisting of 4, 5 and 6-input LUTs.

关键词： Field programmable gate arrays (FPGA)

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Overview of Cryo-CMOS Devices and circuits for Quantum Computing Applications 9

Overview of Cryo-CMOS Devices and Circuits for Quantum Compu...

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9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Manikandan, R.R. Electronics and Communication Engineering Bangalore India

ISBN: (纸本)9798350383249

A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures. © 2023 ieee.

关键词： Temperature

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A Survey on Automatic Assertion Miners

A Survey on Automatic Assertion Miners

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mohammad Reza Heidari Iman Giorgio Di Natale Katell Morin-Allory CNRS Institut National Polytechnique Grenoble Alpes TIMA Univ. Grenoble Alpes Grenoble France

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In the area of functional verification, AssertionBased Verification (ABV) has gained significant attention for the advantages it provides in verifying hardware designs. This approach relies on assertions generated by automatic assertion miners. These miners employ various techniques and methods to automatically mine assertions. This paper focuses on studying the most recent, advanced, and widely used assertion miners in the field and provides an analytical comparison between them. This study aims to highlight the strengths and shortcomings of current automatic assertion miners to assist researchers and verification engineers in understanding the functionality, strengths, and limitations of each miner. By addressing these limitations, more advanced automatic assertion miners can be developed in the future.

关键词： Surveys Focusing Hardware electronic circuits

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Accuracy Enhancement of Resistor-String Digital-to-Analog Converters through Averaging Dynamic Element Matching

Accuracy Enhancement of Resistor-String Digital-to-Analog Co...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Francesco Gagliardi Michele Dei Department of Information Engineering University of Pisa Pisa Italy

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In integrated Digital-to-Analog Converters (DACs), random mismatch errors among nominally equal unit elements significantly limit the achievable accuracy. This work explores the effectiveness of tailored Dynamic Element Matching (DEM) techniques in mitigating mismatch-induced non-linearity errors in resistor-string DAC architectures. Through statistical behavioural simulations, we identify effective DEM strategies that substantially reduce Integral Non-Linearity (INL). The proposed technique enables virtually zero INL errors at specific points of the transfer characteristic, which can be strategically chosen during circuit operation. Insofar, optimized design approaches for resistor-string DACs are proposed, fostering future integratedcircuit implementations with superior yield concerning accuracy and linearity specifications.

关键词： Resistors Accuracy Digital-analog conversion Linearity Integrated circuit modeling electronic circuits

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