This paper addresses a development of electroniccircuitsdesigned for executing fundamental Boolean logic functions based on InAlN/GaN heterostructures. The top-down design flow of the mentioned circuits using an in-...
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ISBN:
(纸本)9781479967803
This paper addresses a development of electroniccircuitsdesigned for executing fundamental Boolean logic functions based on InAlN/GaN heterostructures. The top-down design flow of the mentioned circuits using an in-house fabrication process is described. The front-end design includes the creation of a scalable behavioral model of stand-alone high electron mobility transistors (HEMTs), followed by the design of basic logic cells and circuits. The back-end flow consists of the full-custom design of lithographic masks required for a successful fabrication process. The paper discusses advantages, drawbacks and challenges of the presented procedure as well as expected electrical parameters of the fabricated circuits.
A new approach for erasure codes design with regards to digital multimedia specificity is introduced. The experimental results on coding effectiveness are obtained. Comparison with reference to LT (Luby Transform) cod...
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ISBN:
(纸本)9781424422760
A new approach for erasure codes design with regards to digital multimedia specificity is introduced. The experimental results on coding effectiveness are obtained. Comparison with reference to LT (Luby Transform) codes is performed. The proposed erasure codes allow to achieve more robust decoding for high packet-loss ratios. The designed encoding algorithm is well-fit for hardware parallel processing.
The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires o...
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ISBN:
(纸本)9781424466139
The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires on system bus which varies from 25% up to 81%, while the main disadvantage is increase of the latency of processor read and write operations. The structure of a CDMA wrapper as an interface logic between the shared bus and IP connecting to it is described. VHDL models of two wrapper types (master and slave) are developed and verified. Four different implementations of the CDMA coding technique are presented and realized in FPGA and ASIC technologies.
Verification of embedded systems is a challenge due to the tight combination of hardware and software. We present an approach on the automatic verification of embedded system applications for the operating system Cont...
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ISBN:
(纸本)9781467311854
Verification of embedded systems is a challenge due to the tight combination of hardware and software. We present an approach on the automatic verification of embedded system applications for the operating system Contiki using a standard bounded model checking tool for software. By using an operating system a higher abstraction level to hardware is possible. Our approach is therefore easily applicable for the verification of different hardware platforms.
Approximate Computing (AxC) emerges more and more as a new paradigm for the design of energy-efficient Integrated circuits (ICs) at the cost of accuracy reduction. The latter has to be modeled and quantified by means ...
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ISBN:
(纸本)9781538657546
Approximate Computing (AxC) emerges more and more as a new paradigm for the design of energy-efficient Integrated circuits (ICs) at the cost of accuracy reduction. The latter has to be modeled and quantified by means of Error Metrics. From the testing point of view, AxC Integrated circuits offer an opportunity. Instead of testing for all manufacturing defects, the goal is to test only for those that will lead to an error considered as not acceptable by the adopted Error Metrics. The main advantages are the test cost reduction, since the number of required test vectors will be reduced, and the yield improvement. We developed three approaches for generating test vectors targeting AxC Integrated circuits. This paper aims at comparing these approaches on a public benchmark suite.
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electroniccircuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel desi...
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ISBN:
(纸本)9781424411610
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electroniccircuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. The resulting scan-path elements are fault-tolerant for functional operation and static scan test.
Decoupling capacitance is necessary to stabilize the power distribution network due to the reduced supply voltage and increased current transitions. Decoupling capacitance planning should be a part of design tasks to ...
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ISBN:
(纸本)9781424466139
Decoupling capacitance is necessary to stabilize the power distribution network due to the reduced supply voltage and increased current transitions. Decoupling capacitance planning should be a part of design tasks to minimize the silicon area while maintaining the stability of the power distribution network. This paper shows our study in the on-chip and on-package decoupling capacitors in high-performance microprocessors. At the end, we describe a computer algorithm to optimize the decoupling capacitance allocation based on the power grid analysis.
Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded...
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ISBN:
(纸本)9781424433391
Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded very slow designs. Early output logic is a method which aims to improve the performance of QDI circuits without decreasing their robustness. In order to force QDI restrictions on early output circuits a form of guarding is necessary. This paper presents a new form of guarding which allows partial stage completion allowing desynchronisation of inputs. This is shown to be highly advantageous in cases where the previous style performed poorly. Because the two styles can be mixed, the designs no longer suffer from very poor performance of some QDI constructions.
A new test method using multidimensional search space (TMMSS) for analog electroniccircuits is presented. During test mode the circuit under test is connected to active N-terminal network. The structure and values of...
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ISBN:
(纸本)9781424466139
A new test method using multidimensional search space (TMMSS) for analog electroniccircuits is presented. During test mode the circuit under test is connected to active N-terminal network. The structure and values of elements of this network is selected (by heuristic particle swarm optimization algorithm) in way that the best localization/identification of faults is obtained. The differences between proposed method and others existing methods (specially oscillating testing method) have been described. The proposed method allows to increase observability of the circuit under test, which is very important if integrated circuits are tested. In this paper, the validity of described method has been verified throughout practical myoelectrical filtering circuit (taken from note "Testing Analog and Mixed-Signal Integreted circuits Using Oscillation-Test Method" K. Arabi and B. Kaminska). The obtained simulations results shows, that presented method assure a high degree of localization of CUT faults.
The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable L...
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ISBN:
(纸本)9781479967803
The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable Logic Blocks (CLBs) based on Look Up Tables (LUTs) that may mask a gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck-at faults at the gate poles.
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