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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"
4789 条 记 录,以下是101-110 订阅
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design of InAlN/GaN Heterostructure-based Logic Cells  18
Design of InAlN/GaN Heterostructure-based Logic Cells
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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Nagy, Luka Stopjakova, Viera Satka, Alexander Slovak Univ Technol Bratislava Inst Elect & Photon Bratislava Slovakia
This paper addresses a development of electronic circuits designed for executing fundamental Boolean logic functions based on InAlN/GaN heterostructures. The top-down design flow of the mentioned circuits using an in-... 详细信息
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design of erasure codes for digital multimedia transmitting
Design of erasure codes for digital multimedia transmitting
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11th ieee International Workshop on design and diagnostics of electronic circuits and systems
作者: Shinkarenko, K. V. Vlcek, K. Tomas Bata Univ Nad Stranemi 4511 Zlin 76001 Czech Republic
A new approach for erasure codes design with regards to digital multimedia specificity is introduced. The experimental results on coding effectiveness are obtained. Comparison with reference to LT (Luby Transform) cod... 详细信息
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Wrapper design for a CDMA Bus in SOC
Wrapper Design for a CDMA Bus in SOC
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13th ieee symposium on design and diagnostics of electronic circuits and systems
作者: Nikolic, T. Stojcev, M. Stamenkovic, Z. Univ Nis Fac Elect Engn Nish Serbia IHP GmbH Syst Design Frankfurt Oder Germany
The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires o... 详细信息
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Bounded Model Checking of Contiki Applications
Bounded Model Checking of Contiki Applications
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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Voertler, Thilo Ruelke, Steffen Hofstedt, Petra Fraunhofer Inst Integrated Circuits IIS Design Automat Div EAS Zeunerstr 38 D-01069 Dresden Germany Brandenburg Tech Univ Cottbus Dept Comp Sci D-03013 Cottbus Germany
Verification of embedded systems is a challenge due to the tight combination of hardware and software. We present an approach on the automatic verification of embedded system applications for the operating system Cont... 详细信息
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On the Comparison of Different ATPG approaches for Approximate Integrated circuits  21
On the Comparison of Different ATPG approaches for Approxima...
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21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Traiola, Marcello Virazel, Arnaud Girard, Patrick Barbareschi, Mario Bosio, Alberto Univ Montpellier LIRMM CNRS Montpellier France Univ Naples Federico II DIETI Naples Italy
Approximate Computing (AxC) emerges more and more as a new paradigm for the design of energy-efficient Integrated circuits (ICs) at the cost of accuracy reduction. The latter has to be modeled and quantified by means ... 详细信息
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Flip-flops and scan-path elements for nanoelectronics
Flip-flops and scan-path elements for nanoelectronics
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10th ieee International Workshop on design and diagnostics of electronic circuits and systems
作者: Kothe, R. Vierhaus, H. T. Brandenburg Tech Univ Cottbus Inst Comp Sci POB 10 13 44 D-03013 Cottbus Germany
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electronic circuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel desi... 详细信息
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Decoupling Capacitance Study and Optimization Method for High-Performance VLSIs
Decoupling Capacitance Study and Optimization Method for Hig...
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13th ieee symposium on design and diagnostics of electronic circuits and systems
作者: Zhu, Q. K. Yong, J. Mozdzen, T. Chameleon Syst Inc 7848 Pineville Circle Castro Valley CA 94552 USA
Decoupling capacitance is necessary to stabilize the power distribution network due to the reduced supply voltage and increased current transitions. Decoupling capacitance planning should be a part of design tasks to ... 详细信息
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Forward and Backward Guarding in Early Output Logic
Forward and Backward Guarding in Early Output Logic
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ieee symposium on design and diagnostics of electronic circuits and systems
作者: Brej, Charlie Edwards, Doug Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England
Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded... 详细信息
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Testing Analog electronic circuits using N-terminal Network
Testing Analog Electronic Circuits using N-terminal Network
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13th ieee symposium on design and diagnostics of electronic circuits and systems
作者: Kyziol, Piotr Rutkowski, Jerzy Grzechca, Damian Silesian Tech Univ Inst Elect Gliwice Poland
A new test method using multidimensional search space (TMMSS) for analog electronic circuits is presented. During test mode the circuit under test is connected to active N-terminal network. The structure and values of... 详细信息
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Increasing Manufacturing Yield Using Partially Programmable circuits with CLB implementation of Incompletely Specified Boolean Function of the Corresponding Sub-circuit  18
Increasing Manufacturing Yield Using Partially Programmable ...
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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Matrosova, A. Ostanin, S. Kirienko, I Tomsk State Univ Tomsk Russia
The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable L... 详细信息
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