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design of a Portable and Non-Invasive Hemoglobin Measuring Device 10

Design of a Portable and Non-Invasive Hemoglobin Measuring D...

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10th ieee International symposium on Smart electronic systems, iSES 2024

作者： Maiti, Riya Saha, Srijita Shrivastava, Kriti Midya, Kousik Chattopadhyay, Arnab Dhara, Ashis Kumar National Institute of Technology Electrical Engineering Department Durgapur713209 India ICFAI University Electronics Engineering Department Hyderabad501203 India Institute of Hematology & Transfusion Medicine Medical College Kolkata700073 India

ISBN: (纸本)9798331533229

Detection of Anemia in early stages is very important for proper treatment and clinical trials. There is a dire need of point-of-care screening, early diagnosis and monitoring of Anemia but the laboratory based practices are mostly expensive and technically challenging for middle or low income countries where Anemia is majorly prevalent. The non-invasive measurement method of hemoglobin could be promising alternative as it needs no blood sample, and consequently it is with patient's comfort, minimum infection risk, free from repetitive change of chemicals, and one can monitor in real time. It would also help people staying in remote places through remote diagnostics. This paper presents a non-invasive approach based on transmission spectroscopy, where optical technique has been used to measure Hb concentration with higher accuracy. The proposed device has high potential to be valuable in diagnosis of anemia and its follow up. © 2024 ieee.

关键词： Velocity measurement

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design of a 9.75 - 10.25 GHz Phase Shifter in 180 nm CMOS Process with 360Phase Tunability for Phased Array System 67

Design of a 9.75 - 10.25 GHz Phase Shifter in 180 nm CMOS Pr...

引用

67th ieee International Midwest symposium on circuits and systems, MWSCAS 2024

作者： Patwary, Adnan Basir Mahbub, Ifana University of Texas at Dallas Department of Electrical and Computer Engineering RichardsonTX United States

ISBN: (纸本)9798350387179

To direct the far field radiation beam, phased array antenna systems require electronic phase shifters to supply various input signal phases in the individual elements. In this paper, a three-stage differential phase shifter that is compatible with phased array antenna systems operating at 9.75-10.25 (X band) GHz is proposed. The proposed phase shifter is designed in 180 nm CMOS process and consists of three identical varactor loaded LC stages. A Pi-network topology is used for the single stage phase shifter which consists of a fixed inductor and four varactors. Based on post layout simulation, the inductor value is optimized to include the inductance due to the metal signal lines. The stages are connected via 2-bit PMOS switches which controls the signal flow routes between the stages. The layout of the proposed phase shifter is completed and the signal line length and width connecting the phase-shifted signal to the output are kept the same to assure phase shift accuracy. In order to improve the return loss, input and output matching networks are also designed based on the impedance value from the post layout simulation. The phase response of the phase shifter is controlled using the 6-bit switching of the three stages and fine tuned by controlling the varactor control voltages. The proposed phase shifter achieves 0° - 360° phase shift with almost flat phase response over the 500 MHz bandwidth. © 2024 ieee.

关键词： CMOS integrated circuits

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A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS

A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in...

引用

2024 ieee International symposium on circuits and systems, ISCAS 2024

作者： Lin, Wei-Chung Chang, Yung-Chi Chung, Yung-Hui National Taiwan University of Science And Technology Department of Electronic And Computer Engineering Taipei City Taiwan

ISBN: (纸本)9798350330991

This paper presents a 10-bit two-channel time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) to achieve a maximum sampling rate of 400 MHz in 90-nm CMOS. The channel-ADC incorporates a 2b/cycle-assisted SAR architecture to effectively speed up its operation speed. A new dynamic register is proposed to reduce the DAC control delay. To maintain small capacitor arrays, a multiple-reference C-DAC is applied to avoid using a tiny unit capacitance. This prototype ADC consumes a total power of 3 mW from a 1.2-V supply at 400-MS/s. Measured DNL and INL are -0.77/+1.2 LSB and -1/+1 LSB, respectively. The measured peak SNDR and SFDR are 51 dB and 62.3 dB, respectively. The measured ENOB is 8.2 bits, equivalent to a figure-of-merit of 25.5 fJ/conversion-step. © 2024 ieee.

关键词： CMOS integrated circuits

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Logic Resynthesis of Majority-Based circuits by Top-Down Decomposition 24

Logic Resynthesis of Majority-Based Circuits by Top-Down Dec...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Lee, Siang-Yun Riener, Heinz De Micheli, Giovanni Ecole Polytech Fed Lausanne Integrated Syst Lab Lausanne Switzerland

ISBN: (纸本)9781665435956

Logic resynthesis is the problem of ding a dependency function to re-express a given Boolean function in terms of a given set of divisor functions. In this paper, we study logic resynthesis of majority-based circuits, which is motivated by the increasing interest in majority logic optimization due to the recent. development of beyond-CMOS technologies. To meet the need for an efficient majority resynthesis heuristic, we propose a top-down decomposition algorithm, whose complexity is linear to both n and era, where n is the number of divisors and m is the number of majority operations in the dependency function. We evaluate the resynthesis algorithms by using them in a resubstitution run applied on the EPFL benchmark suite. The experimental results show that, comparing to the state-of-the-art enumeration algorithm whose complexity grows exponentially with m, using the proposed decomposition algorithm leads to 1.5% more circuit size reduction by lifting the limitation on m, within comparable runtime.

关键词： Logic synthesis combinational circuit peephole optimization majority-inverter graph Boolean resubstitution

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Using Model Checker to Analyze and Test Digital circuits with Regard to Delay Faults 24

Using Model Checker to Analyze and Test Digital Circuits wit...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Strnadel, Josef Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781665435956

Narrow timing margins in modern digital circuits result in delay defects that are difficult to detect. The probability that such a defect occurs increases with factors such as shrinking feature sizes, increasing process variations, operating frequencies, and aging/stress of the circuits. Traditionally, timing is considered in connection with the logic design, physical design and layout, and delay testing phases of the circuit development process and builds on principles of delay characterization, fault models and timing analysis. This paper presents a model checking approach aiming to facilitate the solutions of problems with regard to analyzing consequences and testing of delay faults. Our approach expects that a circuit is modeled as a network of stochastic hybrid timed automata capable to describe the circuit both in the logical and temporal domains, including facts such as uncertainty and variations. In our approach, we gather attributes and formalize expected properties of a circuit and transform the circuit into our model. Then, we use a statistical model checker to check the properties and to produce a counter-example for each property being violated. Further, we transform the counter-examples into test cases and finally, into a delay test able to check whether the timing requirements are met.

关键词： digital circuit timing delay fault timed automaton model checking counter-example test case test

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A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis 24

A Parameterizable Chisel Generator of Numerically Controlled...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Damnjanovic, Vukan D. Petrovic, Marija L. Milovanovic, Vladimir M. Univ Kragujevac Fac Engn Sestre Janjic 6 Kragujevac Serbia NOVELIC Veljka Dugosevica 54 Belgrade Serbia

ISBN: (纸本)9781665435956

Numerically controlled oscillators (NCOs) as part of direct digital synthesizers (DDS) are important components in many digital communication subsystems, such as various digital modulation and demodulation schemes, up and down converters, radar, sonar and laser appliances, etc. The vast number of their beneficial characteristics is what makes NCOs so widely used. Taking this into account, a parameterizable generator of numerically controlled oscillators is implemented using Chisel hardware design language. The proposed generator provides a broad range of parameter configurations, such as input and output data types and widths, the number of different output samples, optional use of spur-reducing techniques or different input interfaces, just to name a few. Numerous generated instances have been tested in software simulations and mapped and tested onto a commercial FPGA platform. Obtained results proved that a generator of this kind can legitimately be compared with custom designed NCO modules, both in terms of performance and resource utilization.

关键词： Numerically controlled oscillator direct digital synthesizer Chisel hardware design language design generator

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Fusing EO and LiDAR for SAR Image Translation with Multi-Modal Generative Adversarial Networks

Fusing EO and LiDAR for SAR Image Translation with Multi-Mod...

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2024 ieee International symposium on circuits and systems, ISCAS 2024

作者： Zhu, Jiang Qing, Yuanyuan Lin, Zhiping Wen, Bihan Nanyang Technological University School of Electrical And Electronic Engineering Singapore

ISBN: (纸本)9798350330991

To generate high-quality Synthetic Aperture Radar (SAR) images, the translation of Electro-optical (EO) to SAR images has been studied in recent years. However, these methods cannot make use of other modal information, such as Light Detection and Ranging (LiDAR), to enhance their performance, due to the absence of well-registered multi-modal remote sensing data. Therefore, in this paper, we first construct an organized high-resolution real-world benchmark dataset, which comprises 479 registered multi-modal images. We then explore how to adapt the state-of-the-art method, named the query-selected attention model (QS-Attn), to make it more suitable for integrating EO and LiDAR images into real SAR image translation. Extensive experiments have been conducted to evaluate our proposed method and compare it with state-of-the-art methods. The experimental results validate the superiority and effectiveness of our approach. © 2024 ieee.

关键词： Synthetic aperture radar

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QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware design on RTL

QTFlow: Quantitative Timing-Sensitive Information Flow for S...

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International VLSI symposium on Technology, systems and Applications (VLSI)

作者： Reimann, Lennart M. Prashar, Anshul Ghinami, Chiara Pelke, Rebecca Sisejkovic, Dominik Merchant, Farhad Leupers, Rainer Rhein Westfal TH Aachen Aachen Germany Robert Bosch GmbH Corp Res Gerlingen Germany Newcastle Univ Newcastle Upon Tyne Tyne & Wear England

ISBN: (纸本)9798350360356;9798350360349

In contemporary electronic design Automation (EDA) tools, security often takes a backseat to the primary goals of power, performance, and area optimization. Commonly, the security analysis is conducted by hand, leading to vulnerabilities in the design remaining unnoticed. Security-aware EDA tools assist the designer in the identification and removal of security threats while keeping performance and area in mind. Cutting-edge methods employ information flow analysis to identify inadvertent information leaks in design structures. Current information leakage detection methods use quantitative information flow analysis to quantify the leaks. However, handling sequential circuits poses challenges for state-of-the-art techniques due to their time-agnostic nature, overlooking timing channels, and introducing false positives. To address this, we introduce QTFlow, a timing-sensitive framework for quantifying hardware information leakages during the design phase. Illustrating its effectiveness on open-source benchmarks, QTFlow autonomously identifies timing channels and diminishes all false positives arising from time-agnostic analysis when contrasted with current state-of-the-art techniques.

关键词： quantitative information flow confidentiality hardware security timing channels

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The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies

The Impact of Well-Edge Proximity Effect on PMOS Threshold V...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Marika Grochowska Witold A. Pleskacz Cadence Design Systems Warsaw Poland Warsaw University of Technology Institute of Microelectronics & Optoelectronics Warsaw Poland

This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage $(V_{th})$ in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). The results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 μm or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.

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A 22nm CMOS PFM Buck Converter Used in a 32-Bit RISC-V Microcontroller for IoT Applications 16

A 22nm CMOS PFM Buck Converter Used in a 32-Bit RISC-V Micro...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Oliveira, Luiz H. N. Amaral, Wellington A. Haddad, Sandro A. P. Munoz, Daniel M. Barcelos, Eduardo A. Sotero, Vinicius V. M. Jonhson, Emmanuel K. M. Campagnucci, Pamela R. A. N. Lima, Luis V. N. Electronics Engineering Undergraduate Program Faculty of Gama Brazil Mechatronics Graduate Program University of Brasilia Faculty of Technology Department of Mechanical Engineering DF Brasilia Brazil

ISBN: (纸本)9798331522124

The demand for efficient power management solutions in electronic devices has increased significantly, especially for microcontrollers operating in low-power modes. This article presents the design and implementation of a Pulse Frequency Modulation (PFM)-based buck converter for applications in 32-bit microcontrollers using 22nm CMOS technology. The methodology involves the development of a Constant On Time (COT) architecture that maintains a fixed duration for the activation of the high-side MOSFET, using a monostable multivibrator to generate the necessary timing signals. The converter's performance was simulated under various load conditions and process corners to evaluate its efficiency and output characteristics. The results show that the proposed buck converter achieves high efficiency, with peak values above 95%, while maintaining a low output ripple. Specifically, the converter exhibits an efficiency of 93.4% at a load of 1mA, with output ripple voltages as low as 2.20 mV under ideal conditions. The contributions of this work lie in the advancement of PFM converter technology for modern microcontroller applications, demonstrating the potential of 22nm CMOS processes to improve power efficiency and performance. © 2025 ieee.

关键词： CMOS integrated circuits

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