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Memristors: Device Modeling, design and Verification 9

Memristors: Device Modeling, Design and Verification

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9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Datta, Kamalika Drechsler, Rolf Cyber-Physical Systems Dfki GmbH Bremen Germany Institute of Computer Science University of Bremen Bremen Germany

ISBN: (纸本)9798350383249

In-Memory Computing (IMC) using memristors is considered as one of the most researched topic in recent years. Since the first fabrication of the memristor in 2008, its popularity has expanded to a great extent. Researchers from various diverse domains have explored and contributed to the fabrication and design of the memristor device that in turn aids in the development of crossbar designs for IMC. IMC architectures have the potential to bridge the processor-memory speed gap that exists in current von-Neumann architectures. But due to the variability challenges of the memristive devices being an emerging technology, the technology requires time to mature to be widely adopted by the industry. Research is ongoing and there have been significant efforts from both academia and industry to push this technology forward to the next level. In this paper we aim to provide a brief overview of the various works that have been considered over the last one and a half decade in the broad area of modeling, design, mapping, testing, and verification of the memristor-based circuits and systems. © 2023 ieee.

关键词： Memristors

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Performance Enhancement of 'ARP Block' using 28nm Technology node 9

Performance Enhancement of 'ARP Block' using 28nm Technology...

引用

9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Mahida, Vishal Soni, Bhavesh Ranpura, Nilesh Ganpat University Dept. Electronics and Communication Ahmedabad India EInfochips-An Arrow Company Ahmedabad India

ISBN: (纸本)9798350383249

ASICs, or Application Specific Integrated circuits, are integrated circuits that have been built for a specific usage or application, as the name implies. By decreasing the size of electrical goods and increasing the density of logic gates per chip, ASIC contributed to transform technology. Moore's law states that technology is progressing at a breakneck pace. With the progress of cutting-edge technologies into the deep submicron zone, the performance of integrated circuits is being tested by the aggravation of process variability. To meet timing limitations, physical design engineers employ several EDA tools including as ICC, ICC2, Innovus, PrimeTime, Fusion compiler, and others to optimize power, area, timing, and congestion. Timing optimization solutions must be addressed throughout certain stages of Physical design flow. In this paper, back-end design (PnR) is performed on modules called ARP Block using 28nm technology node. The entire chip is divided into clusters, and each cluster is partitioned into several blocks. ARP Block is the name of the block. We will use several timing optimization tactics to try to improve the overall worst negative slack (Setup Violation) of the timing path group REG2REG at floor-plan stage and placement stage (PNR stages) by implementing 28nm technology in the ICC tool. Nevertheless, relative to the literature survey, we decreased the time violation by 43 percent. © 2023 ieee.

关键词： Application specific integrated circuits

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A Low-Cost Cold Plasma Generator circuits designed for Laboratory Applications 13

A Low-Cost Cold Plasma Generator Circuits Designed for Labor...

引用

13th Latin America symposium on circuits and System (LASCAS)

作者： Diaz, Sergio Guzman, Johan Tenreiro, Claudio Ramirez, Roberto Hernandez, Oscar Univ Talca Electromech Dept Talca Chile Univ Bio Bio Elect & Elect Dept Concepcion Chile

ISBN: (纸本)9781665420082

The generation of cold plasma is applied to different processes as grinding of rocks, hardening of metals and sterilization of food. To obtain cold plasma in a vacuum chamber, it is necessary to partially ionize the gas between the electrodes, generating high voltage pulses of the order of microseconds. The repetition frequencies of these pulses depend on the specific application. The design of the power sources can include a synthetic pulse formation line (PFN) triggered or using vacuum valves or static converter arrays. In laboratory applications where applications for cold plasma are studied, it is convenient for safety to design automatized systems for plasma characterization. This work presents the design of a pulsating source and its attached measurements systems, presenting the procedures and auxiliary circuits for real time plasma characterization on a digital based system.

关键词： Cold plasma Langmuir probes sensors

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Lazy Man’s Resynthesis For Glitching-Aware Power Minimization

Lazy Man’s Resynthesis For Glitching-Aware Power Minimizati...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Andrea Costamagna Xiaoqing Xu Giovanni De Micheli Dino Ruic Google DeepMind Mountain View USA Integrated Systems Laboratory EPFL Lausanne Switzerland

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

This paper presents a novel resynthesis engine for minimizing the dynamic power of digital circuits. Traditional logic synthesis methods primarily focus on zero-delay toggles—logic state changes occurring between the start and end of a clock cycle. In contrast, our engine targets both zero-delay toggles and glitches, unintended transitions within a clock cycle caused by path imbalances. Glitches significantly contribute to power consumption in arithmetic circuits, making their minimization a critical challenge in electronic design. The proposed method uses a database of Pareto-optimal netlists to replace sub-networks in the target circuit with power-efficient alternatives. These replacements are guided by a simulation-driven cost function that evaluates workload-independent switching activity and penalizes gates with high fan-out. We call our approach Lazy Man’s Resynthesis because it builds on an algorithm named Lazy Man’s Synthesis, extending it from technology-independent delay optimization to post-mapping power optimization. Applied to the ISCAS and EPFL benchmarks, our method reduces glitching activity by 4.72% and dynamic power by 9.44%, achieving a 7.61% improvement over the state-of-the-art.

关键词： Power demand Heuristic algorithms Switches Logic gates Minimization Logic Engines electronic circuits Digital circuits Clocks

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Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level 24

Embedded Test Instrument for Intermittent Resistive Fault De...

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ebrahimi, Hassan Kerkhoff, Hans G. Univ Twente Testable Design & Test Integrated Syst TDT Grp Enschede Netherlands

ISBN: (纸本)9781665435956

No-fault-founds (NFFs) threaten the dependability of highly dependable systems in avionic and car industries. Moreover, they drastically increase the test and maintenance costs. One of the main causes of NFFs is intermittent resistive faults (IRFs). IRFs mostly occur due to unstable and marginal interconnections. This paper proposes a new periodic testing method to detect IRFs in interconnections at the chip and the board level. The proposed method is based on on-chip embedded test instruments (ETIs), which are scalable, fully digital, and With a low hardware cost. As a case study, a network-on-chip (NoC) infrastructure with a mesh topology has been utilised. The implementation of the testing method requires a small chip area and power consumption overheads being 3% and 2.5%, respectively. In this paper, first, IRF detection at the chip level has been investigated using simulation-based fault injections in selected interconnections of the NoC. Then, the effectiveness of the proposed method at the board level has been verified by hardware-based fault injections as well as thermal cycling experiments on actual solder joints. The experimental results demonstrated that the on-chip ETIs can be reused effectively to detect IRFs at the board level.

关键词： Intermittent Resistive Fault Intermittent Resistive Fault Detection NetWork-on-chip Board-level Reliability

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Time Delay Compensation to improve the Transient response of Fully Integrated Voltage Regulators in Microprocessors

Time Delay Compensation to improve the Transient response of...

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ieee Conference on Electrical design of Advanced Packaging and systems (ieee EPS EDAPS) - Semiconductor Packaging - The Next Frontier

作者： Kumar, Amit Govindan, Srinivasan Venkataraman, Srikrishnan Schaef, Christopher Seshasayee, Nikhil Intel Technol India Pvt Ltd 1 Xcon Engn Grp Bangalore India

ISBN: (纸本)9798350383768

Modern high-performance server microprocessors are equipped with Fully Integrated Voltage Regulators (FIVR) for generating on-die power domains. FIVR incorporates on-chip power MOSFETs, package inductors, on-die capacitors, and feedback control circuits. It operates as a closed-loop control system, effectively regulating the output voltage amidst load current transients, input voltage fluctuations, and component parameter variations. Like typical feedback control systems, Fully Integrated Voltage Regulators (FIVRs) exhibit inherent time delays, commonly referred to as dead time. These delays have detrimental impacts on both the transient response and stability margins of the FIVR. Our study is centered on assessing how dead time affects a critical transient parameter, such as voltage droop. The minimization of voltage droop is imperative as it directly governs the minimum voltage (Vmin) of the microprocessor. In this paper, a technique is proposed to compensate the effects of time delay in FIVRs to improve the transient response. The proposed model has been validated with examples.

关键词： electronic packages and microsystems Electromagnetic (EM) and EM interference modeling Power integrity and power distribution networks

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Educational project on the design of a demonstrator with automatic pressure measurement

Educational project on the design of a demonstrator with aut...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Zhang, Ming Bournel, Arnaud Raimbault, Jean-Luc Llaser, Nicolas Louis, Nicolas Malatchoumy, Josue Gruat, Daniel Univ Paris Saclay Ctr Nanosci & Nanotechnol C2N CNRS Orsay France LPO Dorian Comp Sci Paris France

ISBN: (纸本)9781665484855

In this paper, the design of a demonstrator with automatic pressure measurement is given. This work is proposed as an educational project with the joint contribution of two French teaching institutions and aims at exploiting a Pirani pressure sensor, conventionally used for very low pressure measurement, for beyond atmospheric pressure measurement. The sensor and the associated electronic interface are designed by students majoring in electronics while students majoring in computer science take in charge the software development for the automatic control of the measurement. The hardware implementation of the pressure demonstrator as well as the associated software development is presented in the paper. Within the developed interactive Graphic User Interface (GUI), three data areas are available: pressure related user command, measured pressure and temperature values in real time, and ongoing transient curves acquisition.

关键词： microelectronics education teaching integrated circuit design information technology

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Robust Built-in Defect-Detection for Low Drop-Out Regulators using Digital Mismatch Injection

Robust Built-in Defect-Detection for Low Drop-Out Regulators...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Saikiran, Marampally Ganji, Mona Chen, Degang Iowa State Univ Dept Elect & Comp Engn Iowa City IA 50011 USA

ISBN: (纸本)9781665484855

The number of electronic components in mission-critical applications is increasing rapidly and, with the dawn of electric vehicles, this increase is expected to accelerate in the near future. As functional safety (FuSa) is of utmost importance in these applications, the increasing demand for integrated circuits with zero defective parts per million (DPPM) is pressing the chip industry to achieve high defect coverage. In this paper, simple digital design for Test (DfT) techniques are presented to detect defects in Low Drop-Out Regulators (LDO). The proposed method uses digital mismatch injection and digital- like detectors to detect various defects in an LDO. The digital nature of the proposed method can help reduce the test cost by avoiding expensive and time-consuming analog testing circuitry. Using spice simulations, we show that our method can detect up to 97.5% of the defects providing high defect-coverage. Additionally, as our injectors and detectors are simple in nature, they are not only area-efficient and easy-to-design but also easily scalable. Furthermore, in this work, we also introduce a simple and robust dual-threshold detector that can be used to monitor faults in biasing circuits.

关键词： Low Drop-Out Regulator defects defect-coverage design for test online-monitoring

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Oximeter for all: An innovative look in inclusive physiological monitoring

Oximeter for all: An innovative look in inclusive physiologi...

引用

2023 ieee Biomedical circuits and systems Conference, BioCAS 2023

作者： Kong, Tianmin Hedayatipour, Ava California State University Dept. of Electrical Engineering Long BeachCA United States

ISBN: (纸本)9798350300260

The market of wearable technology has seen rapid advancements in sensor technology and a growing awareness of the importance of proactive health management in recent years. "Oximeter for all"is a wearable electronic that addresses the common challenges in photoplethysmograph (PPG) sensors, such as motion artifacts, skin pigmentation variation, and environmental factors. Equipped with a dynamic feedback system, this affordable and flexible device ensures accurate blood oxygen measurements regardless of skin pigmentation, ambient light, and temperature variations. Furthermore, the device integrates multiple algorithms for cardiovascular monitoring, sleep conditions, mental stress, and disease diagnostics, providing comprehensive health insights to users. By leveraging advancements in artificial intelligence, machine learning, and cloud computing, the "Oximeter for all"offers personalized data analysis and enhances its capabilities. The device's accuracy, reliability, and user satisfaction make it a promising candidate for partnerships with healthcare providers, research institutions, and technology companies, positioning it as a potential leader in the health monitoring segment of the wearable electronics market. © 2023 ieee.

关键词： CMOS design Entrepreneur Error Correction Inclusive Innovation PPG Pulse Oximeter Skin Pigmentation

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design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet systems 23

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled C...

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23rd International symposium on Quality electronic design (ISQED)

作者： Srinivasa, Srivatsa Rangachar Priya, Jainaveen Sundaram Kurian, Dileep Lozano, Erika Ramirez Yada, Satish Chhabra, Saransh Sahu, Kamakhya Prasad Aseron, Paolo Kalim, Ronald Srinivasan, Anuradha Karnik, Tanay Intel Corp Hillsboro OR USA

ISBN: (纸本)9781665494663

The incentives for chiplet based systems have been multifold with current workloads, heterogeneous integration, and rising cost of technology downscaling. This process is commonly known as die disaggregation where multiple functional chiplets are integrated on an interposer to form a bigger complex system. Current application trends demand these tiled systems to support co-existing chiplets with different technology nodes and different inter-die-interconnect requirements. In this paper, we describe the methodology aspects of co-designing functional chiplets, interposer and package level interconnects. We describe the advantages of chiplet reusability and establishing high throughput inter die connectivity.

关键词： Chiplets heterogenous integration disaggregated systems

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