This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critic...
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ISBN:
(纸本)9781424433391
This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC'99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.
This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ...
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ISBN:
(纸本)9781467361361;9781467361354
This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The imple...
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ISBN:
(纸本)9781479967803
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The implementations include both multiplicative inverse and division. The proposed hardware implementations are designed with high computation speed and throughput. They are oriented for high computation demanding applications with multiple division computations in short sequences.
An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers ...
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ISBN:
(纸本)9781424433391
An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers a conversion gain of 22dB at a clock frequency of 1.5GHz for GALILEO/GPS applications. The design is capable of operating at up to 7GHz with only 3dB gain decrease. The simulated noise figure is 27dB with a power consumption of 730 mu W. Simulations at a supply voltage of 0.9V instead of 1.2V show a gain decrease of only 3dB while the noise figure increases by 2dB.
This paper addresses a development of electroniccircuitsdesigned for executing fundamental Boolean logic functions based on InAlN/GaN heterostructures. The top-down design flow of the mentioned circuits using an in-...
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ISBN:
(纸本)9781479967803
This paper addresses a development of electroniccircuitsdesigned for executing fundamental Boolean logic functions based on InAlN/GaN heterostructures. The top-down design flow of the mentioned circuits using an in-house fabrication process is described. The front-end design includes the creation of a scalable behavioral model of stand-alone high electron mobility transistors (HEMTs), followed by the design of basic logic cells and circuits. The back-end flow consists of the full-custom design of lithographic masks required for a successful fabrication process. The paper discusses advantages, drawbacks and challenges of the presented procedure as well as expected electrical parameters of the fabricated circuits.
In current hardware design flow, functional verification is widely acknowledged as the crucial step. This paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the...
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ISBN:
(纸本)1424401844
In current hardware design flow, functional verification is widely acknowledged as the crucial step. This paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the principal challenges of dynamic verification, by providing a new approach for automatic test generation. This approach combines mutation-based test techniques and genetic algorithms to produce stimuli for design under test. The feasibility of the proposed approach is assessed with a preliminary implementation, and some framework has been tested.
The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires o...
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ISBN:
(纸本)9781424466139
The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires on system bus which varies from 25% up to 81%, while the main disadvantage is increase of the latency of processor read and write operations. The structure of a CDMA wrapper as an interface logic between the shared bus and IP connecting to it is described. VHDL models of two wrapper types (master and slave) are developed and verified. Four different implementations of the CDMA coding technique are presented and realized in FPGA and ASIC technologies.
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electroniccircuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel desi...
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ISBN:
(纸本)9781424411610
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electroniccircuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. The resulting scan-path elements are fault-tolerant for functional operation and static scan test.
Multiple degradation mechanisms limit the lifetime of integrated circuits (ICs). Different aspects can be tackled with design for Reliability approaches already during circuit design to avoid serious implications of d...
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ISBN:
(纸本)9798350332773
Multiple degradation mechanisms limit the lifetime of integrated circuits (ICs). Different aspects can be tackled with design for Reliability approaches already during circuit design to avoid serious implications of degradation for ICs in the field. For example, aging simulations can be performed to investigate the impact of the degradation of integrated transistors onto circuit performance. Since these simulations cause a significant verification effort, we work on approaches to efficiently feed reliability information back to circuit designers. This article discusses these approaches with their application scenarios and benefits.
As transistor dimensions are shrinking into regions of only a few atomic layers, designers are faced with various problems including increased reliability and power issues. Since these problems are amplified by higher...
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ISBN:
(纸本)9781424466139
As transistor dimensions are shrinking into regions of only a few atomic layers, designers are faced with various problems including increased reliability and power issues. Since these problems are amplified by higher circuit temperatures, this paper proposes an approach for the fine-grained modeling of temperature distribution in many-core systems based on Networks-on-Chip. With this model, algorithms can be developed that consider the significant impact of temperature - e.g. on performance, power or reliability. To simulate the dynamic nature of temperature, the thermal properties of according integrated systems are modeled through the instantiation of equivalent RC-circuits. This approach exploits the dualism between electrical and thermal flows of energy. Finally, an application with system control for task mapping and power management exemplifies the proposed simulation methodology.
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