One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count....
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ISBN:
(纸本)1424401844
One-to-All Broadcast (OAB) and All-to-All Broadcast (AAB) [5] group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology [1] using Wormhole (WH) switching.
With the emergence of always-on wireless sensing nodes, AC/DC power conversion solutions for sub 1 W applications are required. Existing approaches are not efficient for such output loads, and therefore, new solutions...
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ISBN:
(纸本)9781728100739
With the emergence of always-on wireless sensing nodes, AC/DC power conversion solutions for sub 1 W applications are required. Existing approaches are not efficient for such output loads, and therefore, new solutions need to be provided. In this paper, we propose a solution that is optimized for operation with output loads up to 500 mW, while high efficiency and close to zero no-load consumption have been our foremost design goals. The proposed design is implemented in a high-voltage CMOS process and transistor level simulation results show improved properties of the proposed solution over the existing ones.
Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using m...
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ISBN:
(纸本)9781424411610
Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using majority gates, we show that a number of faults are un-testable in some implementations, while others are undetected by previously proposed tests, which yield a fault coverage of only 70-80% even in the small circuits examined here. We present a novel test pattern generation algorithm based on the D algorithm and time-frame expansion that can automatically detect all testable stuck-at faults in these families of combinational asynchronous circuits. Finally we present a comparison of the test pattern lengths achieved by this method with previously published full-scan based methods.
This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ...
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ISBN:
(纸本)9781467361361;9781467361354
This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.
The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctn...
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ISBN:
(纸本)9781467311854
The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. The additional functions can be activated under certain conditions by changing control parameters (s...
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ISBN:
(纸本)1424401844
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.
Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniq...
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ISBN:
(纸本)9781479967803
Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniques, which introduce clock skew to distribute the switching activity of the circuit. However, this is typically done at late backend design stages, i.e., in layout after cell placement, which limits the maximum clock phase insertion between the domains. Therefore, we propose a novel preconditioning flow, which considers noise optimization up frontend design, i.e., design coding stage. By this, RTL-level techniques, such as clock inversion, can be applied to further optimize the noise characteristics, while common current shaping strategies can still be applied in the backend design.
This paper presents the construction of a new ball balancing robot (ballbot), together with the design of a controller to balance it vertically around a given position in the plane. Requirements on physical size and a...
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ISBN:
(纸本)9781728100739
This paper presents the construction of a new ball balancing robot (ballbot), together with the design of a controller to balance it vertically around a given position in the plane. Requirements on physical size and agility lead to the choice of ball, motors, gears, omnidirectional wheels, and body frame. The electronic hardware architecture is presented in detail, together with timing results showing that real-time control can be achieved. Finally, we design a linear quadratic regulator for balancing, starting from a 2D model of the robot. Experimental balancing results are satisfactory, maintaining the robot in a disc 0.3 m in diameter.
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate le...
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ISBN:
(纸本)1424401844
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits.
An experimental analog design for parametric test methods efficiency evaluation is presented. The circuit is implemented in a standard 0.35 mu m CMOS process by AMS. The circuit under test (CUT) is a two-stage operati...
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ISBN:
(纸本)9781424422760
An experimental analog design for parametric test methods efficiency evaluation is presented. The circuit is implemented in a standard 0.35 mu m CMOS process by AMS. The circuit under test (CUT) is a two-stage operational amplifier with implemented addressable faults. The control of the overall circuit is ensured by a 7-bit shift register. For higher loading capability a buffer is connected to the output. To preserve the possibility of voltage ramping, the CUT has a separated supply rail. The CUT can be also connected to a feedback network integrated on the chip, and thus, turned into an oscillator.
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