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Three subthreshold flip-flop cells characterized in 90 nm and 65 nm CMOS technology

Three subthreshold flip-flop cells characterized in 90 nm an...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Alstad, Havard Pedersen Aunet, Snorre Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781424422760

This paper examines three different flip-flop designs in subthreshold operation. All flip-flops are simulated in a 65 nm and 90 nm process with a supply voltage ranging from 125 mV to 1 V. Process variations are examined at different process corners. Successful operations of a PowerPC 603 flip-flop at all process corners with a supply voltage down to 125 mV is shown at 65 nm. The best PDP and EDP numbers of flip-flops design at V-DD = 200 mV in this paper are 53.6 aJ and 0.88 yJs, respectively.

关键词： Flip flop circuits

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Normal basis multipliers of general digit width applicable in ECC

Normal basis multipliers of general digit width applicable i...

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Novotny, Martin Schmidt, Jan CTU FEE Prague Dept Comp Sci & Engn Karlovo Nam 13Praha 2 Prague 12135 Czech Republic

ISBN: (纸本)1424401844

We present two architectures of digit-serial normal basis multiplier over GF(2'''). The multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in pubhc-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA.

关键词： Multiplying circuits

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Conversion and Interfacing Techniques for Asynchronous circuits

Conversion and Interfacing Techniques for Asynchronous Circu...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ferringer, Markus Vienna Univ Technol Dept Comp Engn Vienna Austria

ISBN: (纸本)9781424497560

Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In order to obtain a highly optimized circuit implementation, it is often necessary to mix different techniques for exploiting their specific benefits. Consequently, the need for efficient conversion and interfacing techniques between these design methodologies arises. In this paper we take a closer look on how such conversion blocks can be built efficiently. We elaborate implementations for signal conversion between three distinct asynchronous design alternatives, discuss their benefits and drawbacks, and provide simulation results. We not only consider cases where both sender and receiver use handshaking protocols for flow control, but also the situation where this kind of lockstep operation is not possible.

关键词： Delay Latches Logic gates Protocols Receivers Synchronization asynchronous circuits asynchronous circuits asynchronous logic design circuit implementation conversion techniques interfacing techniques logic design

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Modeling Temperature Distribution in Networks-on-Chip using RC-circuits

Modeling Temperature Distribution in Networks-on-Chip using ...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Tockhorn, Andreas Cornelius, Claas Saemrow, Hagen Timmermann, Dirk Univ Rostock Inst Appl Microelect & Comp Engn Rostock Germany

ISBN: (纸本)9781424466139

As transistor dimensions are shrinking into regions of only a few atomic layers, designers are faced with various problems including increased reliability and power issues. Since these problems are amplified by higher circuit temperatures, this paper proposes an approach for the fine-grained modeling of temperature distribution in many-core systems based on Networks-on-Chip. With this model, algorithms can be developed that consider the significant impact of temperature - e.g. on performance, power or reliability. To simulate the dynamic nature of temperature, the thermal properties of according integrated systems are modeled through the instantiation of equivalent RC-circuits. This approach exploits the dualism between electrical and thermal flows of energy. Finally, an application with system control for task mapping and power management exemplifies the proposed simulation methodology.

关键词： Network-on-Chip Temperature Modeling Reliability System control Integrated circuit

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An Efficient Physical design of Fully-testable BDD-based circuits 20

An Efficient Physical Design of Fully-testable BDD-based Cir...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rauchenecker, Andreas Wille, Robert Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria

ISBN: (纸本)9781538604724

For the manufacturing test of ASICs, it is important to reach a high test coverage in order to get the defect level as low as possible. However, complex digital circuits are usually not fully testable. In order to address that, previous work suggested to realize the circuits by means of Binary Decisions Diagrams (BDDs). Here, each node is implemented using multiplexer gates (MUX gates) which, with some minor additions, yield 100% testable circuits with respect to stuck-at and path-delay faults. Unfortunately, current physical implementations of MUX gates are rather expensive with respect to propagation delay, power consumption, or transistor count. Hence, despite the prospect of gaining 100% testability, BDD-based circuits did not find significant attention yet. In this work, we propose an alternative realization of MUX gates based on pass transistor logic which addresses these drawbacks. Experiments show that this allows for the realization of fully testable BDD-based circuits which are competitive to or, in many cases, even better than state-of- the-art realizations.

关键词： Logic gates Transistors Circuit faults Physical design Boolean functions Multiplexing Standards

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Supporting analog design for reliability by efficient provision of reliability information to designers 26

Supporting analog design for reliability by efficient provis...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Gonzalez, Fabio A. Velarde Hahne, Lukas Ortstein, Katrin Lange, Andre Crocoll, Sonja Fraunhofer Inst Integrated Circuits IIS Div Engn Adapt Syst EAS Dresden Germany X FAB Dresden GmbH & Co KG Dresden Germany

ISBN: (纸本)9798350332773

Multiple degradation mechanisms limit the lifetime of integrated circuits (ICs). Different aspects can be tackled with design for Reliability approaches already during circuit design to avoid serious implications of degradation for ICs in the field. For example, aging simulations can be performed to investigate the impact of the degradation of integrated transistors onto circuit performance. Since these simulations cause a significant verification effort, we work on approaches to efficiently feed reliability information back to circuit designers. This article discusses these approaches with their application scenarios and benefits.

关键词： IC reliability transistor degradation design support mission profile

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Functional Verification of Arithmetic circuits: Survey of Formal Methods 25

Functional Verification of Arithmetic Circuits: Survey of Fo...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ciesielski, Maciej Yasin, Atif Dasari, Jiteshri Univ Massachusetts Amherst MA 01003 USA

ISBN: (纸本)9781665494311

This paper gives a brief survey of current stateof-the-art techniques for formal verification of arithmetic circuits with suggestions for future work. In contrast to standard BDD or SAT-based approach that require a reference circuit it concentrates on Symbolic Computer Algebra (SCA) and related techniques that verify the circuits w.r.t. its abstract arithmetic specification. We examine the original computer algebra method;review the algebraic techniques of forward and backward rewriting;and AIG rewriting. We also propose a "hardware rewriting" method, which replaces algebraic rewriting by hardware synthesis of the circuit under verification appended with an inverse of the circuit, expecting it to be reduced to a redundant one.

关键词： Algebra Hardware Standards electronic circuits Arithmetic Formal verification

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PolyAdd: Polynomial Formal Verification of Adder circuits 24

PolyAdd: Polynomial Formal Verification of Adder Circuits

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24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Drechsler, Rolf Univ Bremen Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9781665435956

Only by formal verification approaches functional correctness can be ensured. While for many circuits fast verification is possible, in other cases the approaches fail. In general no efficient algorithms can be given, since the underlying verification problem is NP-complete. In this paper we prove that for different types of adder circuits polynomial verification can be ensured based on BDDs. While it is known that the output functions for addition are polynomially bounded, we show in the following that the entire construction process can be carried out in polynomial time. This is shown for the simple Ripple Carry Adder, but also for fast adders like the Conditional Sum Adder and the Carry Look Ahead Adder. Properties about the adder function are proven and the core principle of polynomial verification is described that can also be extended to other classes of functions and circuit realizations.

关键词： Formal verification

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Automatic and Reliable Electrical Characterization of MOSFETs 17

Automatic and Reliable Electrical Characterization of MOSFET...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Stamenkovic, Z. Vasovic, N. D. Ristic, G. S. IHP GmbH Syst Design Frankfurt Oder Germany Univ Nis Fac Elect Engn Nish Serbia

ISBN: (纸本)9781479945580

A low-cost switching system based on PIC 18F4550 microcontroller, which enables the successive measurement of both electrical characteristics (midgap-subthreshold technique, MGT) and charge-pumping currents (charge-pumping technique, CPT) of metal-oxide-semiconductor field-effect transistor (MOSFET) has been developed. The system can be used for switching between MGT and CPT instead of the expensive commercial switching systems. It has been used for characterization (MGT and CPT measurements) of RADFETs with the oxide thicknesses of 0.4 mu m and 1 mu m.

关键词： midgap-subthreshold technique charge-pumping technique gate oxide charge interface trap switching matrix MOSFET microcontroller

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SOC diagnostic design using RESPIN architecture

SOC diagnostic design using RESPIN architecture

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Mader, Zbynek Jarkovsky, Michal Tech Univ Liberec Halkova 6 Libechov 46117 1 Czech Republic

ISBN: (纸本)1424401844

This paper describes realization of a project that is concerned with a diagnostic system of a SOC. The diagnostic system used RESPIN architecture is based on the ieee 1500 standard and allows testing of cores by compressed test patterns. The patterns for certain core under test are decompressed in the scan chains of the other idle core during the test time. The compressed form of the test patterns is prepared by the algorithm COMPAS and stored in the memory of the SOC. The diagnostic system was implemented to the FPSLIC AT94K circuit that contain FPGA for cores, processor for control test procedure and the memory for storing the compressed test data in one system chip.

关键词： Chip scale packages

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