检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

4,673 篇 会议
120 篇 期刊文献

馆藏范围

4,793 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

2,270 篇 工学
- 1,505 篇 电气工程
- 986 篇 电子科学与技术（可...
- 767 篇 计算机科学与技术...
- 334 篇 软件工程
- 255 篇 信息与通信工程
- 179 篇 控制科学与工程
- 129 篇 仪器科学与技术
- 107 篇 材料科学与工程（可...
- 80 篇 机械工程
- 47 篇 动力工程及工程热...
- 41 篇 生物医学工程（可授...
- 30 篇 光学工程
- 21 篇 化学工程与技术
- 13 篇 冶金工程
- 12 篇 土木工程
- 12 篇 生物工程
- 12 篇 安全科学与工程
- 10 篇 力学（可授工学、理...
486 篇 理学
- 246 篇 物理学
- 225 篇 数学
- 44 篇 系统科学
- 43 篇 统计学（可授理学、...
- 23 篇 化学
- 23 篇 生物学
94 篇 管理学
- 91 篇 管理科学与工程(可...
- 33 篇 工商管理
32 篇 医学
- 31 篇 临床医学
- 11 篇 基础医学(可授医学...
16 篇 经济学
- 16 篇 应用经济学
14 篇 法学
- 11 篇 社会学
6 篇 军事学
4 篇 教育学
1 篇 农学

主题

269 篇 voltage
263 篇 algorithm design...
230 篇 hardware
217 篇 electronic mail
212 篇 frequency
212 篇 circuits
207 篇 circuit simulati...
207 篇 very large scale...
185 篇 energy consumpti...
180 篇 clocks
178 篇 cmos technology
172 篇 switches
168 篇 circuit testing
151 篇 costs
149 篇 electronic circu...
148 篇 design engineeri...
144 篇 computer archite...
141 篇 bandwidth
131 篇 cmos integrated ...
129 篇 design methodolo...

机构

126 篇 school of electr...
57 篇 electronic circu...
43 篇 department of el...
37 篇 electronic circu...
23 篇 department of el...
22 篇 faculty of infor...
19 篇 department of el...
18 篇 group of electro...
16 篇 department of el...
15 篇 school of electr...
14 篇 department of el...
13 篇 department of el...
13 篇 department of el...
13 篇 department of el...
12 篇 department of el...
12 篇 institute of mic...
12 篇 department of el...
12 篇 graduate program...
11 篇 department of el...
10 篇 klipsch school o...

作者

88 篇 k. halonen
43 篇 s. celma
35 篇 s.c. chan
28 篇 b. calvo
27 篇 c. toumazou
22 篇 a. paasio
22 篇 b.j. falkowski
20 篇 e. alarcon
19 篇 n. medrano
19 篇 h. tenhunen
18 篇 chiu-sing choy
18 篇 s. lindfors
16 篇 c. azcona
16 篇 drechsler rolf
15 篇 pantelis georgio...
15 篇 chip-hong chang
14 篇 a. poveda
14 篇 i. kale
14 篇 f. guinjoan
14 篇 asada kunihiro

语言

4,688 篇 英文
69 篇 中文
35 篇 其他
1 篇 葡萄牙文

检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 4793 条记录，以下是141-150 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators

Bridging Quantization and Deployment: A Fixed-Point Workflow...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Obed M. Mogaka Håkan Forsberg Masoud Daneshtalab DeepHERO lab Mälardalen University Sweden Tallinn University of Technology Estonia

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Deploying deep learning models on resource-constrained hardware like Field-Programmable Gate Arrays (FPGAs) remains challenging despite advancements in quantization techniques, which often fail to map optimally to target hardware. This study proposes an end-to-end workflow for fixed-point quantization targeting FPGA accelerators, integrating hardware emulation within quantization-aware training to bridge software-hardware co-design. This ensures quantized models are optimized for real-world deployment. Evaluations on CIFAR-10 and ImageNet datasets using ResNet and VGG models show competitive performance, with up to 2% improvement in accuracy over state-of-the-art methods. This work provides insights to resolve the discrepancies that often occur between software-based quantization and hardware deployment. Our methodology effectively bridges quantization and deployment, providing a practical solution for edge device applications.

关键词： Performance evaluation Deep learning Training Quantization (signal) Image resolution Image edge detection Emulation Bridge circuits Hardware Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Efficient Framework with Sparse Acquisition in CMOS Image Sensors for Low-Power Edge Devices 10

Efficient Framework with Sparse Acquisition in CMOS Image Se...

引用

10th ieee International symposium on Smart electronic systems, iSES 2024

作者： Kisku, Wilfred Kaur, Amandeep Mishra, Deepak Indian Institute of Technology Department of Electrical Engineering Jodhpur India Indian Institute of Technology Department of Computer Science and Engineering Jodhpur India

ISBN: (纸本)9798331533229

Memory bandwidth and power consumption is of utmost importance in the design of low power edge devices. This makes it essential to conserve power both at the sensor node and the computational unit. Our paper proposes a system design methodology to save power by acquiring compressed data at the CMOS Image Sensor (CIS) and making the Convolutional Neural Network (CNN) models lightweight for edge applications. A detailed study highlights the effect of sensor directed sparsity at the CIS, and its effect on CNN models such as VGG-16, MobileNet, ResNet50, EfficientNet, and ResNext models. It provides empirical evidence that the performance is mostly maintained even after pruning and quantization of considered models. The imagenette dataset is used to curate the data with the proposed acquisition pipeline that introduces data sparsity, and the experimental results provide evidence that the proposed pipeline performs at par with conventional CIS acquisition mode. For example, the analysis of VGG-16 model for a sparsity threshold level of 0.2 shows compression of × 7.6, × 16, and × 61 using only pruning (P), only quantization (Q), and with both pruning+quantization (P+Q), respectively. It is also observed that the proposed acquisition pipeline can achieve significant parameter reduction through pruning for model compression, comparable to convectional pipeline. © 2024 ieee.

关键词： CMOS integrated circuits

来源：评论

学校读者我要写书评

暂无评论

electronic design considerations and system development for structural health monitoring with ultrasonic guided waves

Electronic design considerations and system development for ...

引用

ieee International symposium on Applications of Ferroelectrics (ISAF)

作者： Lorenzo Capineri Dipartimento Ingegneria Dell’Informazione Università Degli Studi di Firenze Firenze Italy

ISBN: (数字)9798350371901

ISBN: (纸本)9798350371918

The design of electronic systems for structural health monitoring (SHM) with ultrasonic guided waves (UGW) requires a dedicated electronic front-end considering the peculiarities of this application. The UGW piezoelectric transducers characteristics are first decided depending on the operating environment, the structures material and their dimensions, the definition of connections and transducers diagnostics. Another specific feature of the electronic design is for the systems operating both in passive mode for impact detection and active mode for damage detection and positioning. These two operating modes correspond to different analog electronic chains because the received signals have different amplitude levels and frequency spectrum. The paper will review the main building blocks of the electronic system with a focus on analog front-end electronic circuits.

关键词： Ultrasonic imaging Reviews Pressure vessels Piezoelectric transducers Collaboration Feature extraction Acoustics Monitoring Frequency control electronic circuits

来源：评论

学校读者我要写书评

暂无评论

A Parallel SystemC Virtual Platform for Neuromorphic Architectures 23

A Parallel SystemC Virtual Platform for Neuromorphic Archite...

引用

23rd International symposium on Quality electronic design (ISQED)

作者： Galicia, Melvin Merchant, Farhad Leupers, Rainer Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany

ISBN: (纸本)9781665494663

With the increasing interest in neuromorphic computing, designers of embedded systems face the challenge of efficiently simulating such platforms to enable architecture design exploration early in the development cycle. Executing artificial neural network applications on neuromorphic systems which are being simulated on virtual platforms (VPs) is an extremely demanding computational task. Nevertheless, it is a vital benchmarking task for comparing different possible architectures. Therefore, exploiting the multicore capabilities of the VP's host system is essential to achieve faster simulations. Hence, this paper presents a parallel SystemC based VP for RISC-V multicore platforms integrating multiple computing-in-memory neuromorphic accelerators. In this paper, different VP segmentation architectures are explored for the integration of neuromorphic accelerators and are shown their corresponding speedup simulations compared to conventional sequential SystemC execution.

关键词： electronic System Level Parallel SystemC Simulation Neuromorphic systems Computing-in-Memory

来源：评论

学校读者我要写书评

暂无评论

Performance and Error Tolerance of Stochastic Computing-Based Digital Filter design

Performance and Error Tolerance of Stochastic Computing-Base...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Roshwin Sengupta Ilia Polian John P. Hayes Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany Computer Engineering Laboratory University of Michigan Ann Arbor Michigan USA

Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alternative to traditional deterministic computing for filter design. This paper examines error tolerance, area and power efficiency, and accuracy loss in SC-based digital filters. Specifically, we investigate the impact of various stochastic number generators and increased filter complexity on both FIR and IIR filters. Our results indicate that in an error-free environment, SC exhibits a 49% area advantage and a 64% power efficiency improvement, albeit with a slight loss of accuracy, compared to traditional binary implementations. Furthermore, when the input bit-streams are subject to a 2% bit-flip error rate, SC FIR and SC IIR filters have a much smaller performance degradation (1.3X and 1.9X, respectively) than comparable binary filters. In summary, this work provides useful insights into the advantages of stochastic computing in digital filter design, showcasing its robust error resilience, significant area and power efficiency gains, and trade-offs in accuracy compared to traditional binary approaches.

关键词：

来源：评论

学校读者我要写书评

暂无评论

QPUF: Quantum Physical Unclonable Functions for Security-by-design of Industrial Internet-of-Things 9

QPUF: Quantum Physical Unclonable Functions for Security-by-...

引用

9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Bathalapalli, Venkata K. V. V. Mohanty, Saraju P. Pan, Chenyun Kougianos, Elias University of North Texas Dept. of Computer Science and Engineering United States University of Texas Dept. of Electrical Engineering Arlington United States University of North Texas Dept. of Electrical Engineering United States

ISBN: (纸本)9798350383249

This work presents a Quantum Computing based Physical Unclonable Functions (PUF) architecture with a novel approach for PUF key generation and noise reduction in noisy Quantum systems. The motivation is to explore the potential of Quantum Computing assisted cybersecurity for Security-by-design (SbD) of Industrial-Internet-of-Things (IIoT). Internet-of-Things (IoT) in Industry 4.0 can improve efficiency, increase automation, and facilitate intelligent decision making through the integration of edge cloud computing paradigms. However, the lack of standardization of security protocols across IIoT devices can be challenging due to the heterogeneous nature of these devices. In this context, a novel Quantum circuits based PUF design that is built on real Quantum hardware is presented. The proposed QPUF can facilitate security in IIoT by using a Quantum hardware generated PUF key as the device identity. The proposed PUF design is built using Quantum Hadamard Gate, and Ry gates and has been experimentally demonstrated on IBM Quantum hardware systems. The proposed architecture also supports PUF key generation from Quantum hardware for security applications. Figures-of-merits (FoM) of PUF have been evaluated and presented to demonstrate the robustness of the proposed Quantum PUF for SbD of IIoT. © 2023 ieee.

关键词： Internet of things

来源：评论

学校读者我要写书评

暂无评论

Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration 24

Enhanced Reliability of Fully Differential Difference Amplif...

引用

24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Maljar, David Sovcik, Michal Arbet, Daniel Stopjakova, Viera Slovak Univ Technol Bratislava Inst Elect & Photon Fac Elect Engn & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781665435956

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20 degrees C to 85 degrees C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 mu V to 167 mu V). The concept proposed in this work utilizes advanced high precision calibration algorithm.

关键词： digital calibration PVTA variations high reliability high precision compensation input offset voltage ultra-low voltage design

来源：评论

学校读者我要写书评

暂无评论

An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri Nets

An Efficient Approach for STLs Development of Automotive SoC...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Ernesto Cristopher Villegas Castillo Felipe Augusto Da Silva Michael Glaβ Cadence Design Systems Munich Germany Insritute of Embedded Systems/Real-Time Systems Ulm University Ulm Germany

One of the biggest concerns of Automotive System-on-Chip (SoC) design is the strict safety requirements for their hazardous operative scenarios. Commonly, designers employ Safety Mechanisms (SMs) to mitigate the fault effects and improve the SoC's safety levels. During the development phases, metrics, such as the Fault coverage (FC), are used to validate the effectiveness of the SMs. However, achieving such metrics, as defined by automotive standards, demands additional verification steps, resorting to extensive Fault Injection (FI) campaigns. These usually require mature design stages (e.g., RT-Gate level) involving significant simulation times and several iterations until obtaining the desired FC. Therefore, there is a high demand for new methodologies enabling FC estimation, supporting early-stage exploration, and avoiding expensive redesign phases. This work proposes a methodology exploiting Colored Generalized Stochastic Petri Nets (CGSPN) to model the SoC's architecture at a high level for FC estimation. The method optimizes and reduces the FI campaigns and is intended as a powerful tool supporting the development cycles of SMs, e.g., Software Test Libraries (STLs). Our experiments on an automotive test case indicate that STLs can be validated at a high level with minimal accuracy loss (1.1% on average) by optimizing the fault list in 28%. The results also showed a meaningful speedup of up to 160x in the development process of STLs.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Optimization of CFET Standard Cell Using Double-Cell-Height Structure

Optimization of CFET Standard Cell Using Double-Cell-Height ...

引用

2024 International VLSI symposium on Technology, systems and Applications, VLSI TSA 2024

作者： Huang, Liang-Chi Lu, Ko-Cheng Kang, Wei-Cheng Juan, Bo-Hsun Chu, Pen-Yi Lu, Chih-Hsuan Chang, Tzu-Hsuan National Taiwan University Graduate School of Advanced Technology Taipei Taiwan National Taiwan University Graduate Institute of Electronics Engineering Taipei Taiwan National Taiwan University Department of Electronic Engineering Taipei Taiwan

ISBN: (纸本)9798350360349

CFET presents a promising structure for reducing the routing length of interconnections and, consequently, minimizing the footprint of circuits. However, the strategy of complementarily stacking pFETs and nFETs has encountered significant routing challenges within the already limited floor space. In this study, we demonstrate that mitigating the routing congestion of CFET can be achieved by implementing the double-cell-height strategy in the design of the standard library. This approach enables the optimization of routing capability and length, resulting in an average reduction of 26%. © 2024 ieee.

关键词：

来源：评论

学校读者我要写书评

暂无评论

S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors

S4V: A Benchmark Suite of Transient Execution Attacks for RI...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Elia Lazzeri Matteo Colella Gianluca Furano Luca Cassano Politecnico di Milano Milano Italy European Space Agency Noordwijk The Netherlands

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Transient Execution Attacks (TEAs) exploit architectural optimizations in modern processors, such as out-of-order and speculative execution, to illicitly access sensitive data belonging to other processes or the operating system. While the RISC-V ISA has gained significant traction, its susceptibility to TEAs remains relatively unexplored. A major obstacle to in-depth security evaluation of RISC-V processors is the lack of readily accessible and comprehensive TEA implementations for these architectures. This paper introduces Security for RISC-V (S4V), a security benchmark suite comprising implementations of several recent TEAs specifically tailored for RISC-V processors. Beyond providing a template for each TEA implementation, we developed an instance of S4V for the Berkeley Out-of-Order Machine (BOOM) processor to demonstrate the feasibility of executing these attacks on a widely adopted and renowned RISCV core. S4V aims to facilitate security research in evaluating countermeasures and enabling a more thorough understanding of TEA vulnerabilities within the RISC-V ecosystem.

关键词： Out of order Program processors Operating systems Microprocessors Hardware security Benchmark testing Transient analysis electronic countermeasures Optimization electronic circuits

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共480页 << < 11 12 13 14 15 16 17 18 19 20 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：