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QPUF: Quantum Physical Unclonable Functions for Security-by-design of Industrial Internet-of-Things 9

QPUF: Quantum Physical Unclonable Functions for Security-by-...

引用

9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Bathalapalli, Venkata K. V. V. Mohanty, Saraju P. Pan, Chenyun Kougianos, Elias University of North Texas Dept. of Computer Science and Engineering United States University of Texas Dept. of Electrical Engineering Arlington United States University of North Texas Dept. of Electrical Engineering United States

ISBN: (纸本)9798350383249

This work presents a Quantum Computing based Physical Unclonable Functions (PUF) architecture with a novel approach for PUF key generation and noise reduction in noisy Quantum systems. The motivation is to explore the potential of Quantum Computing assisted cybersecurity for Security-by-design (SbD) of Industrial-Internet-of-Things (IIoT). Internet-of-Things (IoT) in Industry 4.0 can improve efficiency, increase automation, and facilitate intelligent decision making through the integration of edge cloud computing paradigms. However, the lack of standardization of security protocols across IIoT devices can be challenging due to the heterogeneous nature of these devices. In this context, a novel Quantum circuits based PUF design that is built on real Quantum hardware is presented. The proposed QPUF can facilitate security in IIoT by using a Quantum hardware generated PUF key as the device identity. The proposed PUF design is built using Quantum Hadamard Gate, and Ry gates and has been experimentally demonstrated on IBM Quantum hardware systems. The proposed architecture also supports PUF key generation from Quantum hardware for security applications. Figures-of-merits (FoM) of PUF have been evaluated and presented to demonstrate the robustness of the proposed Quantum PUF for SbD of IIoT. © 2023 ieee.

关键词： Internet of things

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Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration 24

Enhanced Reliability of Fully Differential Difference Amplif...

引用

24th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Maljar, David Sovcik, Michal Arbet, Daniel Stopjakova, Viera Slovak Univ Technol Bratislava Inst Elect & Photon Fac Elect Engn & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781665435956

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20 degrees C to 85 degrees C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 mu V to 167 mu V). The concept proposed in this work utilizes advanced high precision calibration algorithm.

关键词： digital calibration PVTA variations high reliability high precision compensation input offset voltage ultra-low voltage design

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An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri Nets

An Efficient Approach for STLs Development of Automotive SoC...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Ernesto Cristopher Villegas Castillo Felipe Augusto Da Silva Michael Glaβ Cadence Design Systems Munich Germany Insritute of Embedded Systems/Real-Time Systems Ulm University Ulm Germany

One of the biggest concerns of Automotive System-on-Chip (SoC) design is the strict safety requirements for their hazardous operative scenarios. Commonly, designers employ Safety Mechanisms (SMs) to mitigate the fault effects and improve the SoC's safety levels. During the development phases, metrics, such as the Fault coverage (FC), are used to validate the effectiveness of the SMs. However, achieving such metrics, as defined by automotive standards, demands additional verification steps, resorting to extensive Fault Injection (FI) campaigns. These usually require mature design stages (e.g., RT-Gate level) involving significant simulation times and several iterations until obtaining the desired FC. Therefore, there is a high demand for new methodologies enabling FC estimation, supporting early-stage exploration, and avoiding expensive redesign phases. This work proposes a methodology exploiting Colored Generalized Stochastic Petri Nets (CGSPN) to model the SoC's architecture at a high level for FC estimation. The method optimizes and reduces the FI campaigns and is intended as a powerful tool supporting the development cycles of SMs, e.g., Software Test Libraries (STLs). Our experiments on an automotive test case indicate that STLs can be validated at a high level with minimal accuracy loss (1.1% on average) by optimizing the fault list in 28%. The results also showed a meaningful speedup of up to 160x in the development process of STLs.

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Optimization of CFET Standard Cell Using Double-Cell-Height Structure

Optimization of CFET Standard Cell Using Double-Cell-Height ...

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2024 International VLSI symposium on Technology, systems and Applications, VLSI TSA 2024

作者： Huang, Liang-Chi Lu, Ko-Cheng Kang, Wei-Cheng Juan, Bo-Hsun Chu, Pen-Yi Lu, Chih-Hsuan Chang, Tzu-Hsuan National Taiwan University Graduate School of Advanced Technology Taipei Taiwan National Taiwan University Graduate Institute of Electronics Engineering Taipei Taiwan National Taiwan University Department of Electronic Engineering Taipei Taiwan

ISBN: (纸本)9798350360349

CFET presents a promising structure for reducing the routing length of interconnections and, consequently, minimizing the footprint of circuits. However, the strategy of complementarily stacking pFETs and nFETs has encountered significant routing challenges within the already limited floor space. In this study, we demonstrate that mitigating the routing congestion of CFET can be achieved by implementing the double-cell-height strategy in the design of the standard library. This approach enables the optimization of routing capability and length, resulting in an average reduction of 26%. © 2024 ieee.

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A Low-Power Level-2 Discrete Haar Wavelet Transform with Approximate Adders for ECG Signal 16

A Low-Power Level-2 Discrete Haar Wavelet Transform with App...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Seidel, Henrique Da Rosa, Morgana Lopes, Rodrigo Da Costa, Eduardo Soares, Rafael Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil

ISBN: (纸本)9798331522124

We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-established approximate adders (AxPPA, COPY, ETA-I, LOA, and Trunc) and bit truncation (T), to reduce energy consumption while maintaining accuracy above 99% for reliable R-peak detection. By focusing on the second-level detail coefficient (D2) for peak detection and pruning the approximation coefficient, the PDHWT-2 design achieves significant reductions in computational complexity. The architecture, evaluated with ECG signals from the MIT-BIH database, maintained accuracy above 99% even with aggressive bit truncation and approximation, ensuring reliable medical-grade analysis. Integration of approximate adders (AxAs) and truncation enabled significant power and area savings. Specifically, the use of the AxPPA demonstrated power savings of up to 40% with area reductions of around 45%, making the PDHWT-2 a highly efficient solution for low-power ECG monitoring systems. © 2025 ieee.

关键词： Image reconstruction

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S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors

S4V: A Benchmark Suite of Transient Execution Attacks for RI...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Elia Lazzeri Matteo Colella Gianluca Furano Luca Cassano Politecnico di Milano Milano Italy European Space Agency Noordwijk The Netherlands

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Transient Execution Attacks (TEAs) exploit architectural optimizations in modern processors, such as out-of-order and speculative execution, to illicitly access sensitive data belonging to other processes or the operating system. While the RISC-V ISA has gained significant traction, its susceptibility to TEAs remains relatively unexplored. A major obstacle to in-depth security evaluation of RISC-V processors is the lack of readily accessible and comprehensive TEA implementations for these architectures. This paper introduces Security for RISC-V (S4V), a security benchmark suite comprising implementations of several recent TEAs specifically tailored for RISC-V processors. Beyond providing a template for each TEA implementation, we developed an instance of S4V for the Berkeley Out-of-Order Machine (BOOM) processor to demonstrate the feasibility of executing these attacks on a widely adopted and renowned RISCV core. S4V aims to facilitate security research in evaluating countermeasures and enabling a more thorough understanding of TEA vulnerabilities within the RISC-V ecosystem.

关键词： Out of order Program processors Operating systems Microprocessors Hardware security Benchmark testing Transient analysis electronic countermeasures Optimization electronic circuits

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Millimeter-wave GaAs Rectifier with Differential Signal 4:1 Power Combiner for Simultaneous Wireless Information and Power Transmission 16

Millimeter-wave GaAs Rectifier with Differential Signal 4:1 ...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Kikuchi, Masayuki Ide, Michihiro Mayeda, Jill Kato, Sena Yuasa, Keito Okada, Kenichi Shirane, Atsushi Institute of Science Tokyo Dept. Electrical and Electronic Engineering 2-12-1-S3-28Ookayama Meguro-ku Japan

ISBN: (纸本)9798331522124

This paper presents a rectifier with a power combiner for a millimeter-wave wireless power transmission system. The proposed circuit uses a diode fabricated in a 0.1 um GaAs process for rectification and mixing, and a metal layer create a transformer to synthesize the power. The rectifier and power synthesizer are integrated into a single chip. The chip has four input ports for 24 GHz WPT differential signals and 25 GHz RF differential signals, and one output port for DC and 1 GHz IF single-ended signals. The DC output can operate with a 100Ω load. For power generation, the most efficient DC conversion is achieved at 25.4GHz signal, where with a total input power of 26.2 dBm, DC conversion efficiency is 10.8%. The maximum DC power obtained is 51.8mW. As a mixer, it achieves a down-conversion gain of -15.6 dB. © 2025 ieee.

关键词： Antenna phased arrays

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Exploring Approximate Adders for Accuracy- and Energy-Quality VLSI Watermarking systems design 16

Exploring Approximate Adders for Accuracy- and Energy-Qualit...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Da Rosa, Morgana Da Costa, Eduardo Soares, Rafael Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil

ISBN: (纸本)9798331522124

Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves exploring different approximation adder (AxA) configurations as a viable form of reducing power consumption in many applications. This work explores the use of AxAs in a hybrid watermarking technique that combines discrete Haar-Wavelet (DHWT) and discrete cosine transforms (DCT). The proposed hybrid method, HyDHWCT, integrates these transforms to improve robustness and imperceptibility in watermarking systems while optimizing for energy efficiency. We evaluate the performance of various AxAs, including Copy, ETA, LOA, Truncation (Trunc), VLSPPAs, and the AxPPA, regarding energy consumption, circuit area, and error resilience. Our results demonstrate that the AxPPA-based HyDHWCT offers superior accuracy and energy-quality trade-offs over other state-of-the-art AxAs. Specifically, the AxPPA on HyDHWCT with K = 1 achieves up to 72.85% energy savings and 88.32% area savings compared to the exact HyDHWCT while maintaining high accuracy, with a normalized cross-correlation (NC) of 0.9949 and a structural similarity (SSIM) of 0.9920 for the extracted watermark. These results make the AxPPA-based HyDHWCT a highly effective solution for robust and energy-efficient watermarking systems. © 2025 ieee.

关键词： Energy efficiency

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Window Function design for Linear Arbitrary Arrays via ICA-ADMM Algorithm

Window Function Design for Linear Arbitrary Arrays via ICA-A...

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2023 International symposium on Signals, circuits and systems, ISSCS 2023

作者： Wei, Wenqiang Yu, Xianxiang Liu, Ruitao Wang, Xiangrong Cui, Guolong University of Electronic Science and Technology of China School of Information and Communication Engineering Chengdu China Beihang University School of Electronic and Information Engineering Beijing China

ISBN: (纸本)9798350342031

In this paper, we propose a novel window function design for linear arbitrary array with constrained gain loss to synthesize beampatterns. Compared with the classical adjustable window functions (CAWFs), the proposed window function can be applied to thinned/sparse array and symmetric/asymmetric beampattern synthesis for multiple steering directions. To this end, the alternating direction method of multipliers (ADMM) is embedded into the iterative convex approximation (ICA) framework to address the resultant nonconvex optimization problem. Finally, numerical results demonstrate the effectiveness of the proposed method in terms of symmetric/asymmetric beampatterns synthesis for thinned/sparse arrays. © 2023 ieee.

关键词： Iterative methods

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Automated design of Sigma-Delta Converters: From Know-How to AI-assisted Optimization 65

Automated Design of Sigma-Delta Converters: From Know-How to...

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ieee 65th International Midwest symposium on circuits and systems (MWSCAS)

作者： de la Rosa, Jose M. Univ Seville CSIC IMSE CNM Inst Microelect Sevilla C Amer Vespucio 28 Seville 41092 Spain

ISBN: (纸本)9781665402798

The design of analog and mixed-signal circuits is based on the well-known top-down/bottom-up methodology, which involves a number of tasks at different abstraction levels of the system hierarchy: from specifications to circuit implementation. Although there have been many efforts to optimize analog synthesis and verification procedures, existing CAD methods and tools are far from an automated design flow, as that commonly used in digital circuits. In this scenario, this talk presents an overview of the automated design and optimization of Analog-to-Digital Converters (ADCs), which are one of the key building blocks in a vast number of digital-driven electronic systems. Without loss of generality, Sigma-Delta Modulators (Sigma Delta Ms) are taken as case study to illustrate the analysis, modeling and design techniques under discussion. Special emphasis is put on how to combine the knowledge derived from state-of-the-art optimization algorithms, with heuristic methods and know-how, as well as recent approaches based on Artificial Intelligence (AI) algorithms, in order to maximize the performance of Sigma Delta M ADCs while keeping computational efficiency high(1).

关键词： Solid modeling Sigma-delta modulation Heuristic algorithms Computational modeling Modulation Artificial intelligence Task analysis

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