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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 4789 条记录，以下是151-160 订阅

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Optimization of Imprecise Multiplier circuits by using Binary Decision Diagram 9

Optimization of Imprecise Multiplier Circuits by using Binar...

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9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Choudhary, Pooja Bhargava, Lava Vinod, G.U. Suhag, Ashok Kumar Fujita, Mashahiro Singh, Virendra Swami Keshvanand Institute of Technology Management and Gramothan Dept. of Electronics and Communication Engineering Jaipur India Malaviya National Institute of Technology Jaipur India Malaviya National Institute of Technology Dept. of Electronics and Communication Engineering Jaipur India Qualcomm Bangalore India Bml Munjal University Dept. of Electronics and Communication Engineering Haryana India Vlsi Design and Education Center University of Tokyo Japan Indian Institute of Technology Dept. of Electrical Engineering Dept. of Computer Science Engineering Bombay India

ISBN: (纸本)9798350383249

Imprecise multipliers are employed to enhance the efficiency and reduce the power consumption of arithmetic circuits while tolerating acceptable levels of inaccuracy in the outcomes. The multiplier circuit has a broader range of applications within embedded systems, particularly in the fields of digital signal processing, IoT and multimedia, etc. We proposed a systematic formal approach utilizing the Look-Up Table (LUT) employing the Burch method to evaluate the imprecise multiplier based on the Binary Decision Diagram (BDD) considering Worst Case Error constraint. Implemented 13 bit multiplier using normal and proposed imprecise multiplier shows 98% reduction in number of nodes. The proposed 25 bit imprecise multiplier based on Burch HL shows an 89% decrement in a number of nodes w.r.t. Burch LH method. BDD generation for imprecise multiplier is 75% faster than normal. © 2023 ieee.

关键词： Timing circuits

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Structured design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations

Structured Design and Evaluation of a Resistor-Based PUF Rob...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Carl Riehm Christoph Frisch Florin Burcea Matthias Hiller Michael Pehl Ralf Brederlow TUM School of Computation Information and Technology Technical University of Munich Munich Germany Fraunhofer AISEC Garching Germany

This paper proposes a new fully CMOS-compatible PUF primitive robust against process variations, supply voltage variations and temperature drift (PVT) based on resistive structures that implements advanced compensation mechanisms already on circuit level. Based on analog simulation data, the PUF is evaluated regarding its unpredictability and its reliability. The results indicate a high quality. Further, a structured approach for designing a suitable error correction is presented to illustrate the whole PUF system.

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CMOS Adaptive Optical Wireless Receiver for Ultra-Low-Power IoT Applications 66

CMOS Adaptive Optical Wireless Receiver for Ultra-Low-Power ...

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Nikseresht, Sasan Fernandez, Daniel Cosp, Jordi Madrenas, Jordi Universitat Politecnica de Catalunya Department of Electronic Engineering Barcelona Spain

ISBN: (纸本)9798350302103

An ultra-low-power adaptive optical wireless receiver comprising integrated photodiodes is presented. The design benefits from a new technique to achieve the modulated input data using a charge pump circuit in a closed-loop connection with a comparator. This method can automatically acquire a reference voltage for comparison and compensate comparator's offset errors and DC-level illumination changes. electronic components and photodiodes are designed in a 0.18 μm Triple-well CMOS technology. Measured waveforms are presented for a pseudo-random stream input data, with a minimum 50 μs pulse width. The receiver's power consumption is 11 pJ/bit for a 20 kb/s data rate and a 0.9 V supply voltage. The proposed design's light beam communication, reduced power consumption, and small area make it suitable for ultra-low-power IoT applications. © 2023 ieee.

关键词： charge pump comparator IoT offset cancellation optical receiver photodiode

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Implementation of Dynamic SISD-SIMD Integer Dividers

Implementation of Dynamic SISD-SIMD Integer Dividers

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Gianluca Radi Ares Tahiraga Robert Kunzelmann Ties Jan Henderikus Kluter Wolfgang Ecker Processor Architecture Laboratory EPFL Lausanne Switzerland Infineon Technologies AG Neubiberg Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Digital division is a pivotal operation in a number of domains, such as scientific computation, cryptography, digital signal processing, and machine learning, and has been broadly researched in the past decades. However, the increasing demand for efficient digital systems has emphasized the design of digital dividers with more stringent area and power costs without excessively compromising their performance. One option to achieve this is to implement Single Instruction Multiple Data (SIMD) dividers capable of exploiting the abundance of data-level parallelism, which is naturally present in common tasks such as stream processing, matrix normalization, and vector scaling. In this paper, we propose the designs of four configurable integer dividers capable of sustaining both Single Instruction Single Data (SISD) and SIMD computations, targeting different levels of performance and efficiency. Compared to one of the state-of-the-art integer dividers, our most efficient SIMD divider shows a 54% smaller area and 30% lower power consumption. Furthermore, we propose a novel technique which can reduce n-bit divisions to smaller (n−m)-bit ones, yielding a peek speedup of 15% when implemented in one of our proposed dividers.

关键词： Costs Power demand Single instruction multiple data Digital systems Machine learning Digital signal processing Frequency conversion Vectors Cryptography electronic circuits

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electronic Quadrature Hybrid Duplexer for Wireless Simultaneous Transmit Receive Operation

Electronic Quadrature Hybrid Duplexer for Wireless Simultane...

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ieee Texas symposium on Wireless and Microwave circuits and systems (WMCS)

作者： Regev, Dror Zolkov, Erez Ginzberg, Nimrod Shilo, Shimi Ezri, Doron Cohen, Emanuel Toga Networks Jerusalem Israel Technion Fac Elect Engn Haifa Israel

ISBN: (数字)9781665486095

ISBN: (纸本)9781665486095

This article presents a new four-port electronic device - the directional quadrature hybrid isolator (DQHI). The topology of this duplexer is similar to the four-arm quadrature hybrid (QH) except for a 90 degrees non-reciprocal phase shifter (NRPS) replacing one of the lambda/4 Z(0) arms. We derive the DQHI S-parameters and show that it performs a 0 degrees/90 degrees power division for an incident signal at port 2 into ports 3 and 4 exactly like a QH, functions as an ideal isolator between ports 1 and 2, enables high-isolation between port 1 to ports 3 and 4 and facilitates injection of self-interference cancellation (SIC) signal from port 4 into 3. Analytic evaluation of a dual-port N-path circuit as an NRPS is performed and the theoretical impact on the DQHI performance is examined. An 8-path, 65-nm NMOS design is utilized to simulate the performance with a 1 GHz clock resulting in 1.7 dB TX-to-antenna loss, antenna-RX loss of 3 dB, SIC-to-RX loss of 6.6 dB, TX-RX and TX-SIC isolations of 26 and 12.5 dB respectively.

关键词： Full-Duplex (FD) Quadrature Hybrid (QH) Quadrature-Quasi Circulating Hybrid (QCQH) electronic-Circulator (EC) Non-Reciprocal Phase Shifter (NRPS) Impedance Transparency

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Bayesian Deep Active Learning for Analog Circuit Performance Classification

Bayesian Deep Active Learning for Analog Circuit Performance...

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ieee International symposium on circuits and systems (ISCAS)

作者： Zhang, Lining Raju, Salahuddin James, Ashish Dutta, Rahul Fournier, Gregoire Lancry, Damien Chuan, Kevin Chai Tshun Chandrasekhar, Vijay Ramaseshan Foo, Chuan Sheng ASTAR Inst Infocomm Res Singapore Singapore ASTAR Inst Microelect Singapore Singapore

ISBN: (纸本)9781665484855

Computationally intensive simulations have made analog circuit sizing challenging for complicated analog circuit performance characterization. Accurate yet computationally efficient data-driven models of circuit performance can potentially accelerate the design and verification process. However, as analog circuits are designed under strict functional and technology constraints, there is a scarcity of data for analog circuit performance classification, posing challenges to data-driven approaches;acquiring more data typically involves running expensive and time consuming simulations. We propose Bayesian Deep Active Learning (BDAL) to learn models using fewer simulations, by iteratively selecting a small number of informative samples to label based on the model uncertainty. Bayesian neural networks used in the BDAL framework are better able to model weight uncertainty while being sufficiently expressive to model complex circuits. Compared with the state-of-the-art approaches, the proposed BDAL method can obtain better classification performance with much fewer number of simulations. Experiments on four diverse analog circuits demonstrate BDAL can achieve significant reduction in data requirement and obtain similar performance with much less labeled data for analog circuit performance classification.

关键词： analog circuit performance classification electronic design automation (EDA) artificial intelligence neural networks active learning

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Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs

Speeding-Up Complex RF IC Sizing Optimizations with a Proces...

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ieee International symposium on circuits and systems (ISCAS)

作者： Vaz, Pedro Gusmao, Antonio Horta, Nuno Lourenco, Nuno Martins, Ricardo Inst Telecomunicacoes Aveiro Portugal Univ Lisbon Inst Super Tecn Lisbon Portugal Univ Evora Evora Portugal

ISBN: (纸本)9781665484855

The automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks in deep nanometer technologies has moved towards process, voltage, and temperature (PVT)-inclusive optimizations, to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations' capabilities to their limits. This paper presents innovative research towards the automation of RF IC design by using deep learning to assist the simulation-based sizing tools in time-consuming PVT-inclusive optimizations. The proposed PVT regressor inputs the circuit's sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. The proposed controlled PVT estimator is tested on a state-of-the-art class C/D voltage-controlled oscillator, reducing the workload of the circuit simulator up to 79% while achieving a speed-up factor of 2.92x, ultimately saving more than 16 days of computational effort.

关键词： Artificial Neural Networks Radio-Frequency Integrated circuits electronic design Automation Deep Learning

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FPGA-Based Hardware-in-the-Loop Real-Time Simulation Implementation 66

FPGA-Based Hardware-in-the-Loop Real-Time Simulation Impleme...

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Kordi, Farshideh Barnard, Christian Fortier, Paul Miled, Amine Université Laval Departement of Electrical and Computer Engineering QuébecQC Canada

ISBN: (纸本)9798350302103

Hardware-in-the-Loop (HIL) simulators have become an essential tool in the automotive industry as they allow comprehensive testing and validation of electronic control units (ECUs), Although HIL simulations are widely used in the vehicle, aerospace and other industries that rely on electronic control systems, they can also be quite challenging to develop. One of the main challenges of HIL simulators is creating a virtual environment that accurately replicates the behavior of the real-world system. Artificial intelligence (AI) algorithms can be trained on extensive real-world datasets to create more accurate virtual environments of complex systems for HIL simulations. Moreover, latency is a crucial factor in producing a reliable virtual environment for ECU in HIL simulations. FPGA (Field Programmable Gate Array) can help to minimize latency in HIL simulations by providing high-performance computing resources. This paper aims to address these challenges by presenting a machine learning-based HIL simulator design on FPGA. The proposed architecture uses FPGA to accelerate the computations of a temporal convolutional neural network (TCN). The paper also describes how increasing the number of input channels can improve the performance of the TCN model on an FPGA. © 2023 ieee.

关键词： anti-lock brake system (ABS) artificial intelligence (AI) electronic control unit (ECU) Hardware-in-the-Loop (HIL) simulator temporal convolutional networks (TCN)

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ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs

ABACUS: ASIP-Based Avro Schema-Customizable Parser Accelerat...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Tobias Hahn Daniel Schüll Stefan Wildermann Jürgen Teich Hardware/Software Co-Design Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Germany

Big Data applications frequently process data streams encoded in semi-structured data formats such as JSON, Protobuf, or Avro. Parsing these data formats into a representation to then be processed by a CPU frequently takes up a major share of the processing time. As a remedy, JSON and Avro FPGA accelerators have been introduced that can parse the data directly in the data path, offloading this workload from the CPU without requiring any additional data movement. However, these accelerators are schema-specific circuits that require time-consuming resynthesis processes for schema adaptations. This is particularly critical in Big Data applications, where multiple schemas may be in use simultaneously. As a remedy, we present an application-specific instruction set processor (ASIP) architecture for parsing Avro data on FPGAs. An instruction program controls the ASIP to parse a specific schema. Any schema change therefore only requires the loading of a new instruction sequence into an instruction memory. It is also shown that this approach is more resource-efficient than related work, as functional units only need to be instantiated once for each Avro data type. Our experimental evaluation shows that we can achieve a throughput of 707–818 MB/s per kLUT which is about 7 to 14 times higher than the throughput per LUT achieved in related work.

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Enhancing an Asynchronous Circuit design Flow to Support Complex Digital System design 35

Enhancing an Asynchronous Circuit Design Flow to Support Com...

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35th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design (SBCCI)

作者： Lemos Sartori, Marcos Luiggi Nunes, Willian Analdo Vilar Calazans, Ney Laert Pontificia Univ Catolica Rio Grande do Sul Polytech Sch GAPH Res Grp Porto Alegre RS Brazil

ISBN: (数字)9781665481281

ISBN: (纸本)9781665481281

Robustness to variations is desirable in current digital circuit design techniques. Sources of variations are many, and the evolution of current integrated circuit fabrication technologies does increase the amount of such sources and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations to one or more variation sources. Asynchronous quasi-delay insensitive design is such a paradigm, providing robustness to process, supply voltage, temperature, ageing and IR drop variations. This paper proposes an enhancement to Pulsar, a recently proposed open source automated flow for the design of quasi-delay insensitive circuits. A new set of abstract components enables the description of choices and decisions about the flow of data tokens inside asynchronous circuits. These components are now available to be used in the design capture phase of Pulsar. To build circuit cells that implement the abstract (synthesis-enabled) components, this paper brings the proposal of the handshaking mutex (HM), a versatile complex gate that eases the design of asynchronous arbiters. Results demonstrate the new flow is more powerful than the baseline version, enabling the automated synthesis of complex asynchronous circuits.

关键词： Asynchronous design electronic design automation Digital circuits Automated synthesis

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