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Normal basis multipliers of general digit width applicable in ECC

Normal basis multipliers of general digit width applicable i...

引用

9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Novotny, Martin Schmidt, Jan CTU FEE Prague Dept Comp Sci & Engn Karlovo Nam 13Praha 2 Prague 12135 Czech Republic

ISBN: (纸本)1424401844

We present two architectures of digit-serial normal basis multiplier over GF(2'''). The multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in pubhc-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA.

关键词： Multiplying circuits

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Test Platform for Fault Tolerant systems design Properties Verification

Test Platform for Fault Tolerant Systems Design Properties V...

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Straka, Martin Miculka, Lukas Kastil, Jan Kotasek, Zdenek Brno Univ Technol Brno 61266 Czech Republic

ISBN: (纸本)9781467311854

In this paper, a methodology for fault tolerant systems design properties verification is presented together with recovery technique for a fault tolerant system after soft errors occurrence in a SRAM-based FPGA. First, the principles of test platform based on an external SEU injector are presented;all components of test platform and their role during SEU simulation are described. Then, a recovery technique based on the generic partial dynamic reconfiguration controller implemented inside an FPGA is presented. The controller is used for the identification of a faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in the FPGA structure as well. The first experiments with a test platform and reconfiguration controller are discussed in this paper.

关键词： Fault tolerant systems design features Controllers MODULE systems Platform permanent fault Reconfiguration Fault tolerance

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design-for-Test Method for High-Speed ADCs: Behavioral Description and Optimization

Design-for-Test Method for High-Speed ADCs: Behavioral Descr...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Lechuga, Y. Mozuelos, R. Martnez, M. Bracho, S. Univ Cantabria Microelect Engn Grp E-39005 Santander Spain

ISBN: (纸本)9781424497560

This paper presents a design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. Then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.

关键词： component Folded and interpolated A/D converters design-for-Test Circuit simulation Behavioral modeling

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SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level designs 23

SHiLA: Synthesizing High-Level Assertions for High-Speed Val...

引用

23rd ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Riazati, Mohammad Daneshtalab, Masoud Sjodin, Mikael Lisper, Bjorn Malardalen Univ Vasteras Sweden

ISBN: (纸本)9781728199382

In the past, assertions were mostly used to validate the system through the design and simulation process. Later, a new method known as assertion synthesis was introduced, which enabled the designers to use the assertions for high-speed hardware emulation and safety and reliability insurance after tape-out. Although the synthesis of the assertions at the register transfer level is proposed and implemented in several works, none of them can be adopted for high-level assertions. In this paper, we propose the SHiLA framework and a detailed implementation guide by which assertion synthesis can also be applied to the high-level design processes. The proposed method, which is fully tool independent, is not only an enabler to highspeed assertion-assisted simulation but can also be used in other scenarios that need assertion synthesis, as it has the minimum possible effect on the main design's performance.

关键词： Assertion Synthesis HLS High-Level design High-Speed Validation

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Conversion and Interfacing Techniques for Asynchronous circuits

Conversion and Interfacing Techniques for Asynchronous Circu...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ferringer, Markus Vienna Univ Technol Dept Comp Engn Vienna Austria

ISBN: (纸本)9781424497560

Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In order to obtain a highly optimized circuit implementation, it is often necessary to mix different techniques for exploiting their specific benefits. Consequently, the need for efficient conversion and interfacing techniques between these design methodologies arises. In this paper we take a closer look on how such conversion blocks can be built efficiently. We elaborate implementations for signal conversion between three distinct asynchronous design alternatives, discuss their benefits and drawbacks, and provide simulation results. We not only consider cases where both sender and receiver use handshaking protocols for flow control, but also the situation where this kind of lockstep operation is not possible.

关键词： Delay Latches Logic gates Protocols Receivers Synchronization asynchronous circuits asynchronous circuits asynchronous logic design circuit implementation conversion techniques interfacing techniques logic design

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Adaptive Input Normalization for Quantized Neural Networks 27

Adaptive Input Normalization for Quantized Neural Networks

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Schmidt, Jan Fiser, Petr Skrbek, Miroslav Czech Tech Univ Dept Digital Design Prague Czech Republic

ISBN: (纸本)9798350359343

Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.

关键词： neural network data preprocessing linear transformation adaptive quantization

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An Efficient Physical design of Fully-testable BDD-based circuits 20

An Efficient Physical Design of Fully-testable BDD-based Cir...

引用

20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rauchenecker, Andreas Wille, Robert Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria

ISBN: (纸本)9781538604724

For the manufacturing test of ASICs, it is important to reach a high test coverage in order to get the defect level as low as possible. However, complex digital circuits are usually not fully testable. In order to address that, previous work suggested to realize the circuits by means of Binary Decisions Diagrams (BDDs). Here, each node is implemented using multiplexer gates (MUX gates) which, with some minor additions, yield 100% testable circuits with respect to stuck-at and path-delay faults. Unfortunately, current physical implementations of MUX gates are rather expensive with respect to propagation delay, power consumption, or transistor count. Hence, despite the prospect of gaining 100% testability, BDD-based circuits did not find significant attention yet. In this work, we propose an alternative realization of MUX gates based on pass transistor logic which addresses these drawbacks. Experiments show that this allows for the realization of fully testable BDD-based circuits which are competitive to or, in many cases, even better than state-of- the-art realizations.

关键词： Logic gates Transistors Circuit faults Physical design Boolean functions Multiplexing Standards

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Functional Verification of Arithmetic circuits: Survey of Formal Methods 25

Functional Verification of Arithmetic Circuits: Survey of Fo...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ciesielski, Maciej Yasin, Atif Dasari, Jiteshri Univ Massachusetts Amherst MA 01003 USA

ISBN: (纸本)9781665494311

This paper gives a brief survey of current stateof-the-art techniques for formal verification of arithmetic circuits with suggestions for future work. In contrast to standard BDD or SAT-based approach that require a reference circuit it concentrates on Symbolic Computer Algebra (SCA) and related techniques that verify the circuits w.r.t. its abstract arithmetic specification. We examine the original computer algebra method;review the algebraic techniques of forward and backward rewriting;and AIG rewriting. We also propose a "hardware rewriting" method, which replaces algebraic rewriting by hardware synthesis of the circuit under verification appended with an inverse of the circuit, expecting it to be reduced to a redundant one.

关键词： Algebra Hardware Standards electronic circuits Arithmetic Formal verification

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Comparing Proton and Neutron Induced SEU Cross Section in FPGA 19

Comparing Proton and Neutron Induced SEU Cross Section in FP...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Vanat, Tomas Krizek, Filip Ferencei, Jozef Kubatova, Hana Czech Tech Univ Fac Informat Technol Dept Digital Design Prague Czech Republic Acad Sci Czech Republ Inst Nucl Phys Dept Nucl Spect Rez Czech Republic

ISBN: (纸本)9781509024674

Single event upsets (SEU) are induced by an electric charge deposited in the material of the chip. The origin of the charge can be either from outside of the chip or it can be generated inside as a result of a nuclear reaction. We have measured the cross section of SEUs in FPGA using protons (directly ionizing particles) and neutrons (indirectly ionizing particles). Used energies up to 34 MeV are in the range, where the differences in the proton's ionizing power are most significant thanks to the Bragg peak. Measurements have shown, that the direct ionization is not the dominant effect causing SEU.

关键词： Field programmable gate arrays (FPGA)

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Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities 20

Logic Testing with Test-per-Clock Pattern Loading and Improv...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Novak, Ondrej Pliva, Zdenek Tech Univ Liberec Studentska 2 Liberec 46117 I Czech Republic

ISBN: (纸本)9781538604724

This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-c1ock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.

关键词： design for testability (DFT) scan-based test linear finite state machines

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