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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs

ABACUS: ASIP-Based Avro Schema-Customizable Parser Accelerat...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Tobias Hahn Daniel Schüll Stefan Wildermann Jürgen Teich Hardware/Software Co-Design Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Germany

Big Data applications frequently process data streams encoded in semi-structured data formats such as JSON, Protobuf, or Avro. Parsing these data formats into a representation to then be processed by a CPU frequently takes up a major share of the processing time. As a remedy, JSON and Avro FPGA accelerators have been introduced that can parse the data directly in the data path, offloading this workload from the CPU without requiring any additional data movement. However, these accelerators are schema-specific circuits that require time-consuming resynthesis processes for schema adaptations. This is particularly critical in Big Data applications, where multiple schemas may be in use simultaneously. As a remedy, we present an application-specific instruction set processor (ASIP) architecture for parsing Avro data on FPGAs. An instruction program controls the ASIP to parse a specific schema. Any schema change therefore only requires the loading of a new instruction sequence into an instruction memory. It is also shown that this approach is more resource-efficient than related work, as functional units only need to be instantiated once for each Avro data type. Our experimental evaluation shows that we can achieve a throughput of 707–818 MB/s per kLUT which is about 7 to 14 times higher than the throughput per LUT achieved in related work.

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Enhancing an Asynchronous Circuit design Flow to Support Complex Digital System design 35

Enhancing an Asynchronous Circuit Design Flow to Support Com...

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35th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design (SBCCI)

作者： Lemos Sartori, Marcos Luiggi Nunes, Willian Analdo Vilar Calazans, Ney Laert Pontificia Univ Catolica Rio Grande do Sul Polytech Sch GAPH Res Grp Porto Alegre RS Brazil

ISBN: (数字)9781665481281

ISBN: (纸本)9781665481281

Robustness to variations is desirable in current digital circuit design techniques. Sources of variations are many, and the evolution of current integrated circuit fabrication technologies does increase the amount of such sources and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations to one or more variation sources. Asynchronous quasi-delay insensitive design is such a paradigm, providing robustness to process, supply voltage, temperature, ageing and IR drop variations. This paper proposes an enhancement to Pulsar, a recently proposed open source automated flow for the design of quasi-delay insensitive circuits. A new set of abstract components enables the description of choices and decisions about the flow of data tokens inside asynchronous circuits. These components are now available to be used in the design capture phase of Pulsar. To build circuit cells that implement the abstract (synthesis-enabled) components, this paper brings the proposal of the handshaking mutex (HM), a versatile complex gate that eases the design of asynchronous arbiters. Results demonstrate the new flow is more powerful than the baseline version, enabling the automated synthesis of complex asynchronous circuits.

关键词： Asynchronous design electronic design automation Digital circuits Automated synthesis

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Stator Imbalance in Asymmetrical Six-Phase Synchronous Motor Drives: High-Resistance Connections and Mismanufactured Winding 14

Stator Imbalance in Asymmetrical Six-Phase Synchronous Motor...

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14th ieee International symposium on diagnostics for Electrical Machines, Power electronics and Drives, SDEMPED 2023

作者： Femia, Antonio Sala, Giacomo Mengoni, Michele Vancini, Luca Rizzoli, Gabriele Zarri, Luca Tani, Angelo University of Bologna Dept. of Electrical Electronic and Information Engineering "G. Marconi" Bologna Italy

ISBN: (纸本)9798350320770

An electric drive can experience a wide variety of faults. Some of them, such as short circuits, can significantly harm the structural integrity of the drive. Others, such as poor connections or manufacturing asymmetries in the stator winding, might not affect the drive integrity but distort the electrical quantities (voltages and currents), causing overheating and imbalances. Improper connections could lead to resistance imbalance, while bad manufacturing may result in some phases having fewer or more turns than expected at the design stage. An analytical approach based on the Vector-Space Decomposition (VSD) is proposed in this paper to model the imbalance resulting from High-Resistance Connections (HRCs) or Manufacturing Defects (MDs) due to a variation in the number of *** study is carried out for a six-phase surface-mounted permanent magnet (SMPM) brushless motor, but it may be extended to any multi-three-phase drive. Finite-element simulations are used to build a realistic model of the electrical machine and confirm the theoretical outcomes. © 2023 ieee.

关键词： Vector spaces

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An FPGA-Based Emulation Platform for Functional Safety Verification in Automotive SoC systems 33

An FPGA-Based Emulation Platform for Functional Safety Verif...

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33rd ieee Asian Test symposium, ATS 2024

作者： Sun, Yutao Wang, Zhijun Huang, Zean Liang, Liping Beijing University of Posts and Telecommunications School of Integrated Circuits Beijing China

ISBN: (纸本)9798331529161

The increasing complexity of automotive SoC systems, particularly in the context of autonomous vehicles, demands rigorous functional safety verification methods. This paper proposes a novel Functional Safety FPGA Fault Injection Tool (FSF-FIT) which builds an FPGA-based emulation platform by using FPGA fault injection techniques. The core innovation of FSFFIT lies in its comprehensive FPGA functional safety evaluation process, targeting specific components within the design Under Test (DUT), down to individual LUTs or registers. This detailed approach allows for accurate reliability level (RL) and diagnostic coverage (DC) assessments of safety mechanisms. The speed and accuracy of FSFFIT were validated through experiments conducted on the XuanTie C906 RISC-V processor as well as on a multiplier with different security mechanisms. The results demonstrated that FSFFIT's performance is consistent with that of SSIM, a certified ISO26262-compliant functional safety tool, while also achieving faster execution times. Additionally, by comparing the results with some state-of-the-art (SOTA) FPGA fault injection tools, our method is superior in terms of injection speed. © 2024 ieee.

关键词： System-on-chip

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Power Efficient Approximate Ternary Subtractor for Image Processing Applications 9

Power Efficient Approximate Ternary Subtractor for Image Pro...

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9th ieee International symposium on Smart electronic systems, iSES 2023

作者： Tharuni, Sangireddy Reddy, Basani Harshavardhan Mamatha, Bhukya Kumar, Uppugunduru Anil Ahmed, Syed Ershad Veeramachaneni, Sreehari Gokaraju Rangaraju Institute of Engineering Technology Department of Electronics and Communication Engineering Hyderabad India Department of Electronics and Communication Engineering Telangana Hyderabad501203 India Bits Pilani Hyderabad Campus Department of Electrical and Electronics Engineering Telangana Hyderabad India

ISBN: (纸本)9798350383249

The ternary logic has been the most popular in recent years. Many ternary logic-based arithmetic circuits, such as adders and multipliers, exist. Applications such as image processing and video processing application, accurate computation is not necessary, approximate computing is employed to significantly improve circuit parameters such as area, power, and power-delay product. This paper presents a design of an efficient 1-bit approximate half subtractor using the k-map-based methodology, which is used to implement a full subtractor and an 8-bit ternary subtractor. In this work, an error is introduced in the difference signal of the half subtractor. The proposed approximate ternary half subtractor show that power and delay are reduced by 42 % and 55 % in comparison with subtractor using 3: 1 multiplexers and are reduced by 37 % and 38% in contrast with subtractor using 2:1 multiplexer. Finally, the proposed 8-bit subtractor is evaluated using an image processing application. © 2023 ieee.

关键词： Computer circuits

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Technical and pedagogical challenges in micronanoelectronics for facing upcoming digital society 13

Technical and pedagogical challenges in micronanoelectronics...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Bonnaud, Olivier Univ Rennes 1 Rennes Inst Elect & Technol NumeR Rennes France GIP CNFM Grenoble France

ISBN: (纸本)9781665420082

The worldwide evolution towards a digital society is strongly underway, thanks in particular to the incredible increase in the performance of electronics and micronanoelectronics in all their compartments, from elementary components to circuits and systems. This accelerating evolution, especially in terms of data flow corresponding to the multiplication of connected objects, raises new challenges of two kinds: technical/technological and human. On the technical side, we need to reduce the size of systems and their energy consumption by controlling elementary devices and circuit architectures. On the human level, we need to adapt skills to the new technical and technological challenges and above all to increase the pool of talent due to the extremely rapid development of applications, despite the growing assistance provided by all the design and manufacturing assistance tools. After having developed the global context, this paper focuses on the different limitations and associated challenges and on the approach brought by the French microelectronics training network for the learning of the know-how in connection with the recovery plans dedicated to the electronics industry.

关键词： electronics circuits and systems micronanoelectronics challenges of connected society electronics engineering education

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Formal Proceedings of the 2016 ieee 19th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2016

Formal Proceedings of the 2016 IEEE 19th International Sympo...

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19th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2016

ISBN: (纸本)9781509024674

The proceedings contain 45 papers. The topics discussed include: system-level reliability evaluation through cache-aware software-based fault injection;a fault injection platform for the analysis of soft error effects in FPGA soft processors;comparison of gate-driven and bulk-driven current mirror topologies;multi-objective BDD optimization for RRAM based circuit design;FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization;a general approach for comparing metastable behavior of digital CMOS gates;hardware implementation of a medium access control layer for industrial wireless LAN;comparative BTI analysis for various sense amplifier designs;impedance calculation based method for ac fault analysis of mixed-signal circuits;co-design of CML IO and interposer channel for low area and power signaling;bioSoC: highly integrated system-on-chip for health monitoring;an effective approach for functional test programs compaction;sequential test decompressors with fast variable wide spreading;built-in self-repair architecture generator for digital cores;and early-stage verification of power-management specification in low-power systems design.

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design of Asynchronous Pipelines with QDI Template Using Commercial FPGA 13

Design of Asynchronous Pipelines with QDI Template Using Com...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Duarte, Gabriel C. Oliveira, Duarte L. Batista, Gracieth C. Inst Tecnol Aeronaut ITA Div Engn Eletron IEEA Sao Jose Dos Campos Brazil

ISBN: (纸本)9781665420082

The asynchronous paradigm has interesting features due to the lack of the clock signal and is another option for project of digital systems. This paradigm has several design styles, where the asynchronous pipeline style is interesting due to its high performance and the simplicity of its control. There are two classes of an asynchronous pipeline: Bundled-data and Quasi Delay Insensitive (QDI). The QDI circuit class is notable for its robustness and high modularity. In this paper, we propose two new asynchronous architectures in the pipeline style for QDI circuits. Unlike many QDI proposals, these architectures focus on platforms FPGA (Field Programmable Gate Array) and VLSI (Very Large-Scale Integration) standard cell. The two new architectures were prototyped in FPGAs devices, applied in a set of benchmarks, and compared with the literature's QDI pipeline architecture, which is also focused on FPGA. From the results obtained by the three architectures, we highlight the increase in throughput of 51.2% of the proposed architecture compared to the literature's architecture.

关键词： QDI asynchronous logic dual-rail code pipeline

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design of a Thermal Battery Dummy with Integrated Sensor Node 32

Design of a Thermal Battery Dummy with Integrated Sensor Nod...

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32nd ieee International symposium on Industrial electronics, ISIE 2023

作者： Grubmuller, Michael Schweighofer, Bernhard Wegleiter, Hannes Graz University of Technology Institute of Electrical Measurement and Sensor Systems Graz Austria

ISBN: (纸本)9798350399714

High-performance Li-ion battery systems require sophisticated thermal management to ensure safe operation and long battery life. Testing such thermal management systems comes with some disadvantages and safety concerns. For this reason, the use of thermal battery dummies is advantageous. In this work, we present the design of a thermal battery dummy with 26650 cylindrical cell geometry with an integrated sensor node. The control of the heating power and the temperature measurement is done inside the dummy cell. Power supply and communication with a test bench computer are done through the supply lines. Thus, the only cell connections are the battery terminals, resulting in a dummy cell with geometric characteristics equivalent to a real Li-ion cylindrical cell. This and an addressing-based communication protocol allows parallel operation of multiple battery dummies in a dummy pack compound. The design of the thermal parameters is based on preceding thermal measurements on a real battery cell;in the following we explain the concept of the thermal dummy and go into more detail on the main electronic circuits. With final measurements on a prototype we show the achieved properties of the thermal dummy. © 2023 ieee.

关键词： Sensor nodes

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AI-Enhanced Codesign of Neuromorphic circuits 66

AI-Enhanced Codesign of Neuromorphic Circuits

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Crowder, Douglas C. Smith, J. Darby Cardwell, Suma G. Sandia National Laboratories Cognitive and Emerging Computing AlbuquerqueNM United States

ISBN: (纸本)9798350302103

Leading neuromorphic computer (NMC) platforms achieve energy efficiency and extreme scalability by implementing simplified models of biological neurons. Future NMCs that rely on complex neuron models for complex calculations will require labor-intensive design processes that are currently performed by highly-trained professionals. In this work, we develop AI-enhanced tools for automating NMC design, demonstrating that such tools can design next-generation circuits. © 2023 ieee.

关键词： AI-enhanced codesign electronic design automation evolutionary algorithms neuromorphic computers reinforcement learning

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