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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"
4789 条 记 录,以下是161-170 订阅
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Normal basis multipliers of general digit width applicable in ECC
Normal basis multipliers of general digit width applicable i...
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9th ieee Workshop on design and diagnostics of electronic circuits and systems
作者: Novotny, Martin Schmidt, Jan CTU FEE Prague Dept Comp Sci & Engn Karlovo Nam 13Praha 2 Prague 12135 Czech Republic
We present two architectures of digit-serial normal basis multiplier over GF(2'''). The multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of ... 详细信息
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Test Platform for Fault Tolerant systems design Properties Verification
Test Platform for Fault Tolerant Systems Design Properties V...
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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Straka, Martin Miculka, Lukas Kastil, Jan Kotasek, Zdenek Brno Univ Technol Brno 61266 Czech Republic
In this paper, a methodology for fault tolerant systems design properties verification is presented together with recovery technique for a fault tolerant system after soft errors occurrence in a SRAM-based FPGA. First... 详细信息
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design-for-Test Method for High-Speed ADCs: Behavioral Description and Optimization
Design-for-Test Method for High-Speed ADCs: Behavioral Descr...
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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Lechuga, Y. Mozuelos, R. Martnez, M. Bracho, S. Univ Cantabria Microelect Engn Grp E-39005 Santander Spain
This paper presents a design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relativ... 详细信息
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SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level designs  23
SHiLA: Synthesizing High-Level Assertions for High-Speed Val...
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23rd ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Riazati, Mohammad Daneshtalab, Masoud Sjodin, Mikael Lisper, Bjorn Malardalen Univ Vasteras Sweden
In the past, assertions were mostly used to validate the system through the design and simulation process. Later, a new method known as assertion synthesis was introduced, which enabled the designers to use the assert... 详细信息
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Conversion and Interfacing Techniques for Asynchronous circuits
Conversion and Interfacing Techniques for Asynchronous Circu...
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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Ferringer, Markus Vienna Univ Technol Dept Comp Engn Vienna Austria
Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In or... 详细信息
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Adaptive Input Normalization for Quantized Neural Networks  27
Adaptive Input Normalization for Quantized Neural Networks
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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)
作者: Schmidt, Jan Fiser, Petr Skrbek, Miroslav Czech Tech Univ Dept Digital Design Prague Czech Republic
Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such... 详细信息
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An Efficient Physical design of Fully-testable BDD-based circuits  20
An Efficient Physical Design of Fully-testable BDD-based Cir...
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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Rauchenecker, Andreas Wille, Robert Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria
For the manufacturing test of ASICs, it is important to reach a high test coverage in order to get the defect level as low as possible. However, complex digital circuits are usually not fully testable. In order to add... 详细信息
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Functional Verification of Arithmetic circuits: Survey of Formal Methods  25
Functional Verification of Arithmetic Circuits: Survey of Fo...
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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Ciesielski, Maciej Yasin, Atif Dasari, Jiteshri Univ Massachusetts Amherst MA 01003 USA
This paper gives a brief survey of current stateof-the-art techniques for formal verification of arithmetic circuits with suggestions for future work. In contrast to standard BDD or SAT-based approach that require a r... 详细信息
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Comparing Proton and Neutron Induced SEU Cross Section in FPGA  19
Comparing Proton and Neutron Induced SEU Cross Section in FP...
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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)
作者: Vanat, Tomas Krizek, Filip Ferencei, Jozef Kubatova, Hana Czech Tech Univ Fac Informat Technol Dept Digital Design Prague Czech Republic Acad Sci Czech Republ Inst Nucl Phys Dept Nucl Spect Rez Czech Republic
Single event upsets (SEU) are induced by an electric charge deposited in the material of the chip. The origin of the charge can be either from outside of the chip or it can be generated inside as a result of a nuclear... 详细信息
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Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities  20
Logic Testing with Test-per-Clock Pattern Loading and Improv...
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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Novak, Ondrej Pliva, Zdenek Tech Univ Liberec Studentska 2 Liberec 46117 I Czech Republic
This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-c1ock offline testing. The test response compaction system is based on a chain of T flip-f... 详细信息
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