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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Implementation of Selective Fault Tolerance with Conventional Synthesis Tools

Implementation of Selective Fault Tolerance with Conventiona...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Augustin, Michael Goessel, Michael Kraemer, Rolf Brandenburg Tech Univ Cottbus Inst Comp Sci Erich Weinert Str 1 D-03046 Cottbus Germany Univ Potsdam Inst Comp Sci D-14482 Potsdam Germany IHP D-15236 Frankfurt Germany

ISBN: (纸本)9781424497560

circuits implementing the concept of Selective Fault Tolerance according to [1] are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. This is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.

关键词： Combinational circuits Fault tolerance Fault tolerant systems Hardware Hardware design languages Optimization Synopsys tool Tunneling magnetoresistance Verilog area redundancy circuit description circuit implementation combinational circuits design tool fault tolerance hardware description languages industrial circuit design logic design redundancy selective fault tolerance

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Adaptive Input Normalization for Quantized Neural Networks 27

Adaptive Input Normalization for Quantized Neural Networks

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Schmidt, Jan Fiser, Petr Skrbek, Miroslav Czech Tech Univ Dept Digital Design Prague Czech Republic

ISBN: (纸本)9798350359343

Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.

关键词： neural network data preprocessing linear transformation adaptive quantization

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design and verification methodology for reconfigurable designs in Atmel FPSLIC

Design and verification methodology for reconfigurable desig...

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Kadlec, Jiri Danek, Martin UTIA AV CR Dept Signal Proc Pod Vodarenskou 4 Prague 18208 8 Czech Republic

ISBN: (纸本)1424401844

Partial dynamic reconfiguration enables designs with increased functional density and lower power consumption, but on the other hand it increases the complexity of the design process. This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description in Matlab / Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating-point IP cores targeting the Atmel AT94K FPSLIC device.

关键词： systems analysis

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Nonlinear Binary Codes and Their Utilization for Test 21

Nonlinear Binary Codes and Their Utilization for Test

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21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Novak, Ondreg Tech Univ Liberec Inst Informat Technol & Elect Liberec Czech Republic

ISBN: (纸本)9781538657546

The nonlinear binary codes have a great disadvantage of difficult enumeration of the results due to the necessity of solving a nonlinear set of equations. In the common case, the computational effort will be equal to the effort of solving a set of nonlinear binary equations with a big number of variables. On the other hand, the nonlinear codes substantially overcome the best parameters of the linear ones. It is possible to design such nonlinear binary cyclic codes that have numbers of individually specified bits substantially bigger than can be obtained for linear ones. In this paper, we discuss properties of built-in pseudo-exhaustive test pattern generators and test compressors that employ the nonlinear binary codes. We elaborate the previous results with new simulations. The results can be used for generator or decompressor structure optimization. We formulate several topics that have to be solved in future to enable practical application of the nonlinear codes in testing.

关键词： BIST design for testability test vector compression technique pseudo-exhaustive testing binary codes

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MDCT IMDCT Low Power Implementations in 90 nm CMOS Technology for MP3 Audio

MDCT IMDCT Low Power Implementations in 90 nm CMOS Technolog...

引用

ieee symposium on design and diagnostics of electronic circuits and systems

作者： Malik, Peter Ufnal, Michal Luczyk, Arkadiusz W. Balaz, Marcel Pleskacz, Witold A. Slovak Acad Sci Inst Informat Bratislava Slovakia Warsaw Univ Technol Inst Microelect & Optoelect PL-00661 Warsaw Poland

ISBN: (纸本)9781424433391

MDCT is the basic processing component for high quality audio compression. It is also the most computationally intensive operation in the vast majority of audio compression standards. Mostly used audio standard for audio compression is still MP3. This paper presents new implementations of five MDCT / IMDCT architectures with different parallelization levels for MP3. Implementation utilize UMC 90 nm CMOS technology. design was optimized for low power applications. Low power libraries and clock gating technique were used for power reduction. All IP cores are capable of computing forward and backward MDCT and this feature makes them universal in multimedia SoCs for accelerating the MP3 audio compression/decompression.

关键词： CMOS integrated circuits

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The influence of global parametric faults on analogue electronic circuits time domain response features

The influence of global parametric faults on analogue electr...

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Jantos, P. Grzechca, D. Golonek, T. Rutkowski, J. Silesian Tech Univ Gliwice Poland

ISBN: (纸本)9781424422760

This paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. The novel approach is the analysis of relations and superrelations between features which are discussed in details. The presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. The recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.

关键词： Analog integrated circuits

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Continuous-time common-mode feedback circuit for applications with large output swing and high output impedance

Continuous-time common-mode feedback circuit for application...

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11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Yan, Weixun Zimmermann, Horst Vienna Univ Technol Inst Elect Measurements & Circuit Design A-1040 Vienna Austria

ISBN: (纸本)9781424422760

Motivated by the fact that no existing common mode feedback block (CMFB) can work for the systems characterized with both high output impedance and large output swing, a new CMFB topology is introduced in this paper to accomplish this task. Various types of CMFB are studied, analyzed and simulated. Compared with other CMFBs, the proposed CMFB obtains the widest linear input range, smallest output common-mode level error, largest (full) output swing and has no interference to the system output impedance. All these properties entitle the presented CMFB circuit to suit all types of fully differential systems, especially for systems which require both high output impedance and large signal output swing.

关键词： Continuous time systems

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Two-level logic synthesis for low power based on new model of power dissipation

Two-level logic synthesis for low power based on new model o...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Brzozowski, I. Kos, A. AGH Univ Sci & Technol Al Mickiewicza 30 PL-30059 Krakow Poland

ISBN: (纸本)9781424411610

Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. Therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.

关键词： CMOS integrated circuits

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The design Features of Low-Temperature Radiation-Hardened Instrumentation Amplifiers and Sensor Interfaces 19

The Design Features of Low-Temperature Radiation-Hardened In...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Titov, A. E. Prokopenko, N. N. Pakhomov, I. V. Southern Fed Univ Rostov Na Donu Russia Don State Tech Univ Rostov Na Donu Russia

ISBN: (纸本)9781509024674

The article gives a theoretical analysis of the generalized structure of precision instrumentation amplifiers (IA) of modern interfaces for sensor and diagnostic systems of robots and unmanned aerial vehicles (UAV), which operate, among others, on exposure to radiation and low temperatures. The main disadvantages of classical IA are determined from the common positions and the possible ways of their clearing are presented. The new architecture of radiation-hardened differential difference op-amp (DDA) based on "folded" cascode is developed for the application in sensor interfaces and its simulation results are given, taking into account the effect of disturbing factors.

关键词： robot sensor interface analog microcircuits instrumentation amplifier neutron flux low temperatures

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Implementation of an Asynchronous Bundled-Data Router for a GALS NoC in the Context of a VSoC 20

Implementation of an Asynchronous Bundled-Data Router for a ...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Russell, Patrick Doege, Jens Hoppe, Christoph Preusser, Thomas B. Reichel, Peter Schneider, Peter Fraunhofer Inst Integrated Circuits HS Div Engn Adapt Syst EAS Erlangen Germany Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781538604724

designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. The developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry.

关键词： network-on-chip low power low latency GALS asynchronous circuits vision-system-on-chip CAD synthesis

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