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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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SREEP: Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan design

SREEP: Shift Register Equivalents Enumeration and Synthesis ...

引用

13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Fujiwara, Katsuya Fujiwara, Hideo Obien, Marie Engelene J. Tamamoto, Hideo Akita Univ Fac Engn & Resource Sci Akita 0108502 Japan Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300192 Japan

ISBN: (纸本)9781424466139

We reported a secure scan design approach using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. The security level of the secure scan architecture based on those shift register equivalents is determined by the probability that an attacker can identify the configuration of the shift register equivalent used in the circuit, and hence the attack probability approximates to the reciprocal of the cardinality of the class of shift register equivalents. In this paper, we clarify the cardinality of each class of shift register equivalents from several linear structured circuits and the cardinality of the whole class of shift register equivalents. We also consider the enumeration problem of shift register equivalents and the synthesis problem of desired shift register equivalents. A program called SREEP (Shift Register Equivalents Enumeration and Synthesis Program) is presented to solve those problems.

关键词： scan design shift register equivalents security testability cardinality enumeration

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Optimization Concepts for Self-Healing Asynchronous circuits

Optimization Concepts for Self-Healing Asynchronous Circuits

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ieee symposium on design and diagnostics of electronic circuits and systems

作者： Panhofer, Thomas Friesenbichler, Werner Delvai, Martin RUAG Aerospace Austria GmbH Austria Institute of Computer Engineering Vienna University of Technology Austria

ISBN: (纸本)9781424433391

Decreasing feature size and lower supply voltage cause integrated circuits to be more error-prone, during production as well as during runtime. At the same time the demand for higher reliability is increasing. In particular for applications with long mission times and where no repair is possible, complex fault tolerance mechanisms are required, leading to a dramatic increase of design and system costs. Runtime reconfiguration seems to be a promising way to obtain a circuit which is able to handle these challenges. In previous papers we presented a self-healing approach based on asynchronous Four-State Logic (FSL) and using reconfigurable circuit elements, called Self-Healing Cells (SHCs). These SHCs allow to bypass defect resources and to recover from multiple permanent faults. While the combinational logic can be easily reconfigured this way, the application of SHCs in an asynchronous pipeline requires special treatment of the handshake signals. In this paper we present a self-healing pipeline architecture and analyse different SHC architectures with respect to resource occupation, fault tolerance and reconfiguration speed.

关键词： Fault tolerance

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Low-voltage low-power highly linear down-sampling mixer in 65nm digital CMOS technology

Low-voltage low-power highly linear down-sampling mixer in 6...

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Schweiger, Kurt Zimmermann, Horst Vienna Univ Technol Inst Elect Measurement & Circuit Design A-1040 Vienna Austria

ISBN: (纸本)9781424422760

A highly linear down-conversion mixer in a 65nm digital CMOS technology is presented. The mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other works not the gate but the bulk connector is used for the input signal. A high IIP3 of +18dBm was achieved with a power consumption of only 0.67mW from a 1.2V supply voltage. The mixer has a measured 1dB compression point of +7dBm. The input signal bandwidth lies beyond 2GHz.

关键词： Mixers (machinery)

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A Methodology to Verify Digital IP's Within Mixed-Signal systems 21

A Methodology to Verify Digital IP's Within Mixed-Signal Sys...

引用

21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Navaneetha, C. M. Breitenreiter, Anselm Ulbricht, Markus Krstic, Milos IHP Syst Design Technol Pk 25 D-15236 Frankfurt Oder Germany Univ Potsdam D-14469 Potsdam Germany

ISBN: (纸本)9781538657546

This paper describes a methodology to improve the quality of verification and an approach to dimension the arithmetic of register transfer level (RTL) model of the digital part of the mixed-signal system. This includes the refinement of the high level model of the system and generation of a MATLAB fixed-point model and test-bench for MATLAB-HDL co-simulation. Additionally an approach for the dimensioning of an adaptive equalizer in frequency domain is discussed. The proposed methodology and results of analysis are applied to verify 10BASE-T/100BASE-TX Ethernet PHY IP.

关键词： 10BASE-T/100BASE-TX Ethernet PHY fixed-point model co-simulation quantization effects system verification methodology test-bench

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VARMA-VARiability Modelling and Analysis Tool

VARMA-VARiability Modelling and Analysis Tool

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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Russell, G. Burns, F. Yakovlev, A. Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

ISBN: (纸本)9781467311854

Process parameter variability in IC manufacturing has become an increasingly important issue as feature scaling descends further into the deep submicron region. Within industry the development of EDA tools associated with 'process-aware-design' has a high priority as the impact on circuit performance due to process variations is having increasingly adverse effects on yield and performance. VARMA is a variability analysis tool which enables optimisation of both manufacturing process and nano-electronic circuit design in order to avoid 'manufacturing surprises' resulting in costly chip respins, delays in reaching the market place and the subsequent loss of profitability.

关键词： VLSI design process variability CAD tools

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Structure-Preserving Modeling of Safety-Critical Combinational circuits 20

Structure-Preserving Modeling of Safety-Critical Combination...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rasim, Feim Ridvan Kocar, Canan Sattler, Sebastian M. Friedrich Alexander Univ Erlangen Nuremberg Chair Reliable Circuits & Syst Paul Gordan Str 5 D-91052 Erlangen Germany

ISBN: (纸本)9781538604724

In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph. For creating a signal flow plan it is necessary to swap the nodes and the edges in the signal flow graph. After executing this action the result is a signal flow plan. A value table exhibits the coding of the whole circuit. Then the so called module view is used to get the familiar compact display and neighborhood relations are repeated once more, the resolution method is used. It is observed that in digital circuits, undefined results can occur but these must be avoided in safety critical circuits. These events have to be secured in practice by costly and expensive verification and testing. In order to deal with the problem now, the structure preserving modeling has to be understood, since this is the only way to achieve a one-purpose, qualitative and cost effective search for errors.

关键词： Combinational circuit structure modeling symbolic analysis signal flow graph Boolean function

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design and simulation of runtime reconfigurable systems

Design and simulation of runtime reconfigurable systems

引用

11th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Pionteck, Thilo Albrecht, Carsten Koch, Roman Brix, Torben Maehle, Erik Med Univ Lubeck Inst Comp Engn D-23538 Lubeck Germany

ISBN: (纸本)9781424422760

This paper presents an architectural framework and simulation model for tile-based runtime reconfigurable systems. The framework accounts for all hardware limitations of actual FPGA devices and is based on the division of the reconfigurable system partition into a set of small tiles. These tiles can either be exchanged individually at runtime or can be grouped to larger tiles and be exchanged as a whole. The adaptive tile size allows the realization of hardware modules of varying sizes. For easing the system design process a SystemC simulation methodology at a high abstraction level is presented which provides support for all architectural features of the hardware framework. In particular, the capability of simulating runtime reconfigurable systems is supported by the simulation methodology without modifying the SystemC kernel. The applicability of the architectural framework and of the simulation model is demonstrated by means of an example.

关键词： systems analysis

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Comparison of Gate-Driven and Bulk-Driven Current Mirror Topologies 19

Comparison of Gate-Driven and Bulk-Driven Current Mirror Top...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Rakus, Matej Stopjakova, Viera Arbei, Daniel Slovak Univ Technol Bratislava Fac Elect Engn & Informat Technol Inst Elect & Photon Bratislava Slovakia

ISBN: (纸本)9781509024674

In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. The achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.

关键词： gate-driven bulk-driven current mirrors output resistance output swing low voltage analog circuits

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Co-design of CML IO and Interposer Channel for Low Area and Power Signaling 19

Co-design of CML IO and Interposer Channel for Low Area and ...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Chaudhary, Muhammad Waqas Heinig, Andy Fraunhofcr Inst Integrated Circuits IIS Design Automat Div EAS D-01069 Dresden Germany

ISBN: (纸本)9781509024674

In recent years, 2.5D integration of ICs on Inter-poser is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.

关键词： Bandwidth

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SiP design Flow and 3D DRC for MEMS 17

SiP Design Flow and 3D DRC for MEMS

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mehdaoui, A. Pagazani, J. Schroepfer, G. Lissorgues, G. Coventor SARL Villebon Sur Yvette France Univ Paris Est ESYCOM UPEMLV ESIEE Paris Paris France

ISBN: (纸本)9781479945580

he contribution will describe in detail recent development related to the integration of MEMS into a SiP design flow. A key step in implementing system-level simulation is the translation of the physical behavior of the constitutive components in a system from the more fine-grained continuum level to more abstract, coarse grained models. An important challenge is the preservation of accuracy from fine-grained simulation to a degree that is deemed adequate. In order for the simulator to run in a reasonable time, the system-level model should only include the degrees of freedom (DOF) necessary to capture the relevant physics. Very handy in this sense are methods of model-order reduction (MOR), which under certain conditions enable almost automatic transfer from the continuum level simulation up to the behavioral models with minimal loss of accuracy.

关键词： Microelectromechanical systems design flow Motor Activity behavioral models simulator optical coherence tomography angiography device system parameter Continuum simulating CONSERVATION

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