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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"
4789 条 记 录,以下是181-190 订阅
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SREEP: Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan design
SREEP: Shift Register Equivalents Enumeration and Synthesis ...
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13th ieee symposium on design and diagnostics of electronic circuits and systems
作者: Fujiwara, Katsuya Fujiwara, Hideo Obien, Marie Engelene J. Tamamoto, Hideo Akita Univ Fac Engn & Resource Sci Akita 0108502 Japan Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300192 Japan
We reported a secure scan design approach using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. The security level of the secure scan architecture based on... 详细信息
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Optimization Concepts for Self-Healing Asynchronous circuits
Optimization Concepts for Self-Healing Asynchronous Circuits
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ieee symposium on design and diagnostics of electronic circuits and systems
作者: Panhofer, Thomas Friesenbichler, Werner Delvai, Martin RUAG Aerospace Austria GmbH Austria Institute of Computer Engineering Vienna University of Technology Austria
Decreasing feature size and lower supply voltage cause integrated circuits to be more error-prone, during production as well as during runtime. At the same time the demand for higher reliability is increasing. In part... 详细信息
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Low-voltage low-power highly linear down-sampling mixer in 65nm digital CMOS technology
Low-voltage low-power highly linear down-sampling mixer in 6...
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11th ieee International Workshop on design and diagnostics of electronic circuits and systems
作者: Schweiger, Kurt Zimmermann, Horst Vienna Univ Technol Inst Elect Measurement & Circuit Design A-1040 Vienna Austria
A highly linear down-conversion mixer in a 65nm digital CMOS technology is presented. The mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other... 详细信息
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A Methodology to Verify Digital IP's Within Mixed-Signal systems  21
A Methodology to Verify Digital IP's Within Mixed-Signal Sys...
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21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Navaneetha, C. M. Breitenreiter, Anselm Ulbricht, Markus Krstic, Milos IHP Syst Design Technol Pk 25 D-15236 Frankfurt Oder Germany Univ Potsdam D-14469 Potsdam Germany
This paper describes a methodology to improve the quality of verification and an approach to dimension the arithmetic of register transfer level (RTL) model of the digital part of the mixed-signal system. This include... 详细信息
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VARMA-VARiability Modelling and Analysis Tool
VARMA-VARiability Modelling and Analysis Tool
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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Russell, G. Burns, F. Yakovlev, A. Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England
Process parameter variability in IC manufacturing has become an increasingly important issue as feature scaling descends further into the deep submicron region. Within industry the development of EDA tools associated ... 详细信息
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Structure-Preserving Modeling of Safety-Critical Combinational circuits  20
Structure-Preserving Modeling of Safety-Critical Combination...
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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Rasim, Feim Ridvan Kocar, Canan Sattler, Sebastian M. Friedrich Alexander Univ Erlangen Nuremberg Chair Reliable Circuits & Syst Paul Gordan Str 5 D-91052 Erlangen Germany
In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph. For creating a signal flow plan it ... 详细信息
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design and simulation of runtime reconfigurable systems
Design and simulation of runtime reconfigurable systems
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11th ieee International Workshop on design and diagnostics of electronic circuits and systems
作者: Pionteck, Thilo Albrecht, Carsten Koch, Roman Brix, Torben Maehle, Erik Med Univ Lubeck Inst Comp Engn D-23538 Lubeck Germany
This paper presents an architectural framework and simulation model for tile-based runtime reconfigurable systems. The framework accounts for all hardware limitations of actual FPGA devices and is based on the divisio... 详细信息
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Comparison of Gate-Driven and Bulk-Driven Current Mirror Topologies  19
Comparison of Gate-Driven and Bulk-Driven Current Mirror Top...
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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)
作者: Rakus, Matej Stopjakova, Viera Arbei, Daniel Slovak Univ Technol Bratislava Fac Elect Engn & Informat Technol Inst Elect & Photon Bratislava Slovakia
In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no ... 详细信息
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Co-design of CML IO and Interposer Channel for Low Area and Power Signaling  19
Co-design of CML IO and Interposer Channel for Low Area and ...
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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)
作者: Chaudhary, Muhammad Waqas Heinig, Andy Fraunhofcr Inst Integrated Circuits IIS Design Automat Div EAS D-01069 Dresden Germany
In recent years, 2.5D integration of ICs on Inter-poser is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this... 详细信息
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SiP design Flow and 3D DRC for MEMS  17
SiP Design Flow and 3D DRC for MEMS
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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Mehdaoui, A. Pagazani, J. Schroepfer, G. Lissorgues, G. Coventor SARL Villebon Sur Yvette France Univ Paris Est ESYCOM UPEMLV ESIEE Paris Paris France
he contribution will describe in detail recent development related to the integration of MEMS into a SiP design flow. A key step in implementing system-level simulation is the translation of the physical behavior of t... 详细信息
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