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Biologically Plausible Learning on Neuromorphic Hardware Architectures 66

Biologically Plausible Learning on Neuromorphic Hardware Arc...

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Wolters, Christopher Taylor, Brady Hanson, Edward Yang, Xiaoxuan Schlichtmann, Ulf Chen, Yiran Duke University Department of Electrical and Computer Engineering DurhamNC United States Institute for Electronic Design Automation Technical University of Munich Munich Germany

ISBN: (纸本)9798350302103

Movement of model parameters from memory to computing elements in deep learning (DL) has led to a growing imbalance known as the memory wall. Neuromorphic computation-in-memory (CIM) is an emerging paradigm that addresses this imbalance by performing computations directly in analog memory. However, sequential backpropagation of error through a network in DL prevents efficient parallelization. A novel method, direct feedback alignment (DFA), resolves layer dependencies by directly passing the error from the output to each layer. This work explores the interrelationship of implementing a bio-plausible learning algorithm like DFA in-situ on neuromorphic CIM hardware, emphasizing energy, area, and latency constraints. Using the DNN+NeuroSim benchmarking framework, we investigate the impact of hardware nonidealities and quantization on algorithm performance, as well as how network topologies and algorithm-level design choices scale latency, energy, and area consumption of a chip. While standard backpropagation learns more accurate models when faced with hardware imperfections, DFA enables significant speedup through parallelization, reducing training time by a factor approaching N for N-layer networks. © 2023 ieee.

关键词： Compute-in-memory deep neural network direct feedback alignment hardware/software co-design

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Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design

Ultra-Thin-Body and Buried Oxide FD-SOI next generation node...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Claire Fenouillet-Beranger Laurent Fesquet Rihab Chouk Gabriel Pares Baudoin Martineau Marie-Claire Cyrille Thierry Poiroux Olivier Billoint Dominique Noguet CEA-Leti Univ. Grenoble Alpes Grenoble France CNRS Grenoble INP TIMA Université Grenoble Alpes Grenoble France

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

The European FAMES Pilot Line addresses a set of technologies including fully depleted silicon-on-insulator technology advanced nodes and embedded non-volatile memories. This paper addresses these two technologies and the programs planned to help designers to use these technologies at their best. The specific electrical properties of FD-SOI devices, are discussed, both in terms of transistor modelling and process highlighting the levers exploited to boost the performance of the future 10-7nm nodes will be also highlighted. The paper also address embedded Non-Volatile Memory (eNVM) devices integrated in the BEOL of advanced FD-SOI CMOS technologies with the aim to open opportunities for disruptive IC architectures and designs using the most appropriate eNVM for the considered applications. OxRAM, FeRAM, BEOL FeFET and MRAM are addressed in FAMES and in the paper and potential new applications are discussed. Finally, the way these technologies are provided to designers through training programs is described.

关键词： Training Hands Nonvolatile memory Ferroelectric films Random access memory Europe Silicon-on-insulator Transistors FeFETs Strain

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Study of an OPTO-ASIC for a Functionally Safe Speed Sensor Using the Spatial Frequency Filter Method

Study of an OPTO-ASIC for a Functionally Safe Speed Sensor U...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Frank Wasinski Werner Bonath Ubbo Ricklefs Michael Schwarz Josef Börcsök Dept. of Electrical Engineering and Information Technology THM University of Applied Sciences Giessen Germany ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

For decades, speed sensors based on the spatial frequency filter method have successfully proven themselves in a wide range of applications. This makes the sensor concept particularly suitable for the area of functional safety. New filter variants extend the previous measuring range to very low speeds up to standstill detection. By combining the sensor with a safety system on chip for recording and analysing measured values, a functionally safe measuring chain can be established. In order to demonstrate the variability and performance of the new filters, an optical application-specific integrated circuit was designed, which forms the basis for further extensive tests. The core components are a large number of freely configurable photodiode channels, which were realised via a redundant structure, as well as two different transimpedance amplifier concepts. In the further course of the project, the ASIC will be analysed with regard to its desired performance parameters and its robustness.

关键词： Optical filters Semiconductor device measurement Optical design Stimulated emission Safety Topology System-on-chip Optical sensors Optical amplifiers Velocity measurement

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HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model, Testbench and EDA Project Generation 34

HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog...

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34th International Workshop on Rapid System Prototyping - Shortening the Path from Specification to Prototype

作者： Morgan, Fearghal Byrne, John Patrick Bupathi, Abishek George, Roshan Elahi, Adnan Callaly, Frank Kelly, Sean O'Loughlin, Declan Univ Galway Galway Ireland Trinity Coll Dublin Dublin Ireland

ISBN: (纸本)9798400704109

This paper presents the open source HDLGen-ChatGPT application, working in tandem with ChatGPT-3.5, the free online large language model (LLM) chat interface. The tools enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus electronic design Automation (EDA) projects. EDA tools check the generated HDL syntax, simulate and synthesise HDL models, and follow the steps to FPGA hardware prototyping. The tools exploit a formal, top-down design and test specification documentation process, domain knowledge, and the flexibility of LLMs, for HDL code generation. Results are included for a hierarchical RV32I RISC-V processor design. Process steps are illustrated for the RISC-V 32 x 32-bit register bank component. The process typically requires only minimal manual HDL capture or editing, and often none at all. URLs to tutorial videos for the complete RISC-V design are provided on the GitHub project repository. The paper evaluates the results and provides HDLGen-ChatGPT and ChatGPT usage recommendations. The tools can be applied in digital systems training programmes, with reduced emphasis on the assessment of HDL model and testbench capture and generation, while maintaining strong emphasis on the assessment of system design, test planning and documentation, HDL simulation verification/debug, and analysis of synthesised netlists.

关键词： Digital systems design HDLGen-ChatGPT LLM ChatGPT Generative AI design Capture Automation HDL EDA FPGA testbench VHDL Verilog

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Towards an Automated Debugging Approach for Fault Identification in Quantum circuits

Towards an Automated Debugging Approach for Fault Identifica...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Anton Maidl Abhoy Kole Kamalika Datta Jannis Stoppe Rolf Drechsler Institute for the Protection of Maritime Infrastructure German Aerospace Center (DLR e.V.) Bremerhaven Germany Institute of Computer Science University of Bremen Bremen Germany Cyber-Physical Systems DFKI GmbH Bremen Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In this paper, we propose a novel method for locating and diagnosing bugs in quantum circuits. Debugging in the quantum domain is especially challenging due to the inherent inability of assessing the quantum state of a program. Moreover, explaining the root cause behind unexpected outcomes is hard due to the limited information gain provided by measurements. Our approach aims to address both of these issue: Firstly, the bug site is identified using a standard circuit slicing technique combined with an associated measurement strategy. Secondly, we provide information about the nature of the bug, generated through repeated measurements. To minimize the number of measurements, we introduce a notion of equivalence classes based on unitary operations. This allows us to partition the gate library into classes that produce indistinguishable results under certain measurements. Finally, We assess the effectiveness and measurement complexity of our method by applying it to relevant primitive gate components and well-known quantum algorithms. Our empirical results shows that in 95.79% of all cases, our approach reveals the correct location of the bug along with a valid set of fault candidates. Furthermore, we demonstrate that the required number of circuit executions scales logarithmically with the circuit depth or linearly with the number of qubits.

关键词： Accuracy Computer bugs Qubit Debugging Logic gates Search problems Libraries Circuit faults Quantum circuit Standards

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Characterization of Interconnect Fault Effects in SRAM-based FPGAs

Characterization of Interconnect Fault Effects in SRAM-based...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Christian Fibich Martin Horauer Roman Obermaisser Dept. of Electronic Engineering UAS Technikum Wien Vienna Austria Chair for Embedded Systems University of Siegen Siegen Germany

The configurable interconnect of SRAM-based FPGAs makes up a significant portion of their configuration, and thus exposes a large attack surface to single-event upsets. A better understanding of the behavior of FPGA interconnects under the presence of these faults may allow fault injection campaigns and reliability estimation techniques to treat some interconnect faults as more serious than others. This work proposes an approach to (1) analyze the interconnect configuration of a given FPGA technology to deduce the logical effects caused by single-bit flips and (2) to characterize the effects of such faults on routes implemented on a given FPGA technology. These approaches are illustrated in case studies on two FPGA technologies: Xilinx 7 Series and Lattice iCE40. Characterization of interconnect faults on these devices revealed that certain subcategories of interconnect fault types are far more critical than others, allowing more focused fault injection campaigns. Applying this knowledge to three benchmark designs implemented on a Xilinx 7 Series device shows that fault injection effort can be significantly reduced by skipping bits that are unlikely to critically impact the design.

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design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-compute...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Hussien Abdo Jan Lappas Mohammadreza Esmaeilpour Christian Weis Norbert Wehn University of Kaiserslautern-Landau (RPTU) Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

High-speed memory interfaces require the design of optimised low-power and robust analog circuits. This poses significant challenges in sizing due to the inability of using complex modern transistor models, such as the Berkeley Shortchannel IGFET Model (BSIM), to calculate the sizing of the circuits based on hand-analysis. This forces designers to perform iterative simulations, which is time-intensive and error-prone. To address these issues, this work presents an automated sizing approach using pre-computed lookup tables (LUTs) for a 4.3 Gb/s LPDDR4X transceiver in 12nm FinFET technology. The receiver is designed based on g m /I D sizing methodology where look-up tables are used to compute a set of matrices representing the possible design points based on the circuit topology. The design space is constrained by the biasing level, gain, and bandwidth to find an optimised design point in terms of operation region, speed and power. The driver circuit design is automated based on a new algorithm which computes the estimated ON-resistance from the look up table and finds an optimum sizing which fulfills the required impedance range. The calculated sizing of the proposed design approach was used as an input for spectre simulator to compare the simulation results with the input specifications, showing an error margin of less than 1%. Furthermore, the receiver power consumption was evaluated to be 70% less than the work in literature. The proposed driver topology, which uses low voltage swing terminated logic (LVSTL) and near-ground signaling (NGS), provides a 38−120Ω impedance range at all process, voltage and temperature variations (PVT) for the postlayout results and consumes relatively low power when compared to literature.

关键词： Power demand Simulation Receivers Voltage FinFETs Transceivers Table lookup Topology Impedance Transistors

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Voltage-to-Voltage Sigmoid Neuron Activation Function design for Artificial Neural Networks 13

Voltage-to-Voltage Sigmoid Neuron Activation Function Design...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Moposita, Tatiana Trojman, Lionel Crupi, Felice Lanuzza, Marco Vladimirescu, Andrei Sorbonne Univ ISEP Inst Super Elect Paris Paris France Univ Calabria DIMES Arcavacata Di Rende Italy

ISBN: (纸本)9781665420082

An Artificial Neural Network (ANN) involves a complex network of interconnected nodes called artificial neurons (AN);the AN sums N weighted inputs and send thought the result to a non-linear activation function (AF). In this work, a modified version of the sigmoid activation function is proposed. To obtain a voltage-to-voltage (V-V) transfer function required by an specific ANN. The proposed solution uses a pseudo-differential pair configuration at the input as voltage to current converter. The proposed circuit is designed using a commercial PDK in 180nm (TSMC) and is simulated in Virtuoso (Cadence). This specific design enable to obtain the desired steepness of the sigmoid function by means of the proper transistor sizing. Simulation results of our specific design show that we can reach an average relative error of only 1.09 % for steepness of 1 as compared to the exact mathematical function, and a power consumption of 6.77 mu W for steepness of 10.

关键词： Artificial Neural Network non-linear transfer function sigmoid activation function pseudo differential pair

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PPA Based CNN Architecture Explorer 13

PPA Based CNN Architecture Explorer

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13th Latin America symposium on circuits and System (LASCAS)

作者： Shahshahani, Masoud Bhatia, Dinesh Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

ISBN: (纸本)9781665420082

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly popular for implementing convolutional neural networks (CNNs) due to their low latency and high energy efficiency. In practice, a software designer first explores various CNN architectures in software to improve architecture's validation accuracy. Once an architecture is finalized, the designer must build a computation core on an FPGA for inference acceleration. The requirement of FPGA Performance, Power consumption, and Area (or resources) (PPA) is affected by many CNN model parameters, accelerator topology, and classification accuracy for a CNN implementation. However, the CNN mapping design space is enormous, and efficient mapping of CNN can quickly become a challenging task. Therefore, an exploration tool is essential for building a reconfigurable, fast, and efficient hardware accelerator. We have presented an integrated methodology for exploring FPGA-based CNN architectures by making tradeoffs between the performance, power, and area. This methodology becomes a mapping aid for software engineers who can evaluate the effect of CNN design on the implementation and performance of FPGA-based CNN accelerators.

关键词： FPGAs Accelerators Convolutional Neural Networks design Space Explorer

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Smart devices and RFID: towards an Android-based information system in the cattle-yards 13

Smart devices and RFID: towards an Android-based information...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Sapriza, Juan Arnaud, Alfredo Bellini, Bruno Estevez, Felipe Miguez, Matias Univ Catolica Uruguay Av 8 Octubre 2738 Montevideo 11600 Uruguay BQN Technol Paysandu 1371 Montevideo 11200 Uruguay

ISBN: (纸本)9781665420082

The main change being observed in the use of Radio Frequency Identification (RFID) tools within the cattle industry is not related to the technology itself like hardware or protocols. Instead, is to incorporate RFID as part of the information system combined with a cattle database, not only to be compliant with mandatory traceability requirements, but also to increase productivity;the more on-site information the more efficiency to take decisions on individual animals. In this work, the evolution of a Low Frequency RFID (LF-RFID) stick reader named Baqueano from a simple traceability tool, towards the first Android RFID stick reader aimed at the cattle industry, is presented.

关键词： RFID circuits & systems for agribusiness Android devices

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