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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Proceedings of the 2014 ieee 17th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2014

Proceedings of the 2014 IEEE 17th International Symposium on...

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17th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2014

ISBN: (纸本)9781479945580

The proceedings contain 65 papers. The topics discussed include: automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems;design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications;SiP design flow and 3D DRC for MEMS;studying DAC capacitor-array degradation in charge-redistribution SAR ADCs;automatically connecting hardware blocks via light-weight matching techniques;a double-path intra prediction architecture for the hardware H.265/HEVC encoder;online test vector insertion: a concurrent built-in self-testing (CBIST) approach for asynchronous logic;quality assurance in memory built-in self-test tools;fast time-parallel C-based event-driven RTL simulation;lower bounds of the size of shared structurally synthesized BDDs;BuildMaster: efficient ASIP architecture exploration through compilation and simulation result caching;and analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators.

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2013 ieee 16th International symposium on design and diagnostics of electronic circuits & systems (DDECS) [Copyright notice]

2013 IEEE 16th International Symposium on Design and Diagnos...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to ieee Copyrights Manager, ieee Operations Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. Copyright (c) 2013 by ieee. ieee Catalog Number: CFP13DDE-ART. ISBN: 978-1-4673-6136-1.

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Feasible All-Optical OR and NOR Logic Gates in Photonic Crystals 16

Feasible All-Optical OR and NOR Logic Gates in Photonic Crys...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Novy, Gabriel Felipe Candido Alves, Julio Cesar Teodoro Ramirez, Jhonattan Cordoba Neto, Omar Paranaiba Vilela Belo Horizonte Brazil Belo Horizonte Brazil Belo Horizonte Brazil

ISBN: (纸本)9798331522124

This work presents the design and simulation of photonic crystal-based OR and NOR logic gates, aimed at eliminating the need for dynamic control signals dependent on input combinations. Utilizing silicon-based photonic crystals operating at a 1550 nm wavelength, the gates exhibit enhanced performance, making them suitable for optical computing. Simulation results confirm the reliability of the proposed designs, with the OR and NOR gates achieving contrast ratios of 5.3 dB and 5.1 dB, respectively. Innovative waveguide junctions play a crucial role in minimizing signal loss and preserving signal integrity. This work advances photonic computing by offering a simplified control mechanism while maintaining high performance, paving the way for more energy-efficient and faster alternatives to traditional electronic logic gates. Future research directions include experimental validation and integration into more complex photonic circuits. © 2025 ieee.

关键词： Logic design

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Controllability-Based Circuit Similarity Estimation

Controllability-Based Circuit Similarity Estimation

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Michal Žáček Petr Fišer Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Prague Czech Republic

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Assessing the structural similarity of different implementations of logic functions is of importance in many areas of digital design, such as iterative resynthesis, engineering change order (ECO) based design, design of reliable redundant systems (duplex, TMR), etc. In general, numerous metrics exist that describe such similarity, mostly based on its intended application. In this paper, we introduce a novel metric based on a calculation of the functional equivalence of subcircuits. As this approach requires repeated calls of time-consuming functional equivalence checking, we propose a linear-time approximation of this method based on signal controllability calculation. These two approaches are compared to the state-of-the-art fault detection-based design diversity estimation technique and applied to assess the fault-security capabilities of duplex systems.

关键词： Measurement Fault detection Estimation Reliability engineering Logic functions Electrical fault detection Controllability Iterative methods Integrated circuit reliability electronic circuits

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Duality and resonance in RLC–circuits. Exact formulas for phase, amplitude resonance and bandwidth

Duality and resonance in RLC–circuits. Exact formulas for p...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Daniel Blokhin Institute of Engineering and Information Technologies Kyiv National University of Technologies and Design Kyiv Ukraine

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

The paper is devoted to the study of two-terminal electric circuits consisting of three elements - a resistor, a capacitor, and an inductor. There are eight different possible combinations of such circuits. We apply a standard and nonstandard duality (frequency duality). In this way, all possible circuits are divided into three groups: (2+ 2 +4). The first pair of circuits is extensively covered in most electrical engineering textbooks. The second pair is not interesting from the frequency point of view. We investigate in detail a third group of four circuits, which, by suitable substitution of variables, bring the finding of their frequency characteristics to the study of a single function. For them we find exact formulas for the frequency of phase resonance and amplitude resonance. The values of the minimum (maximum) amplitude at the corresponding resonance frequencies are found. Exact and approximate formulas for the cut-off frequency and bandwidth of the passband-stopband transition are derived.

关键词： Resistors circuits Resonant frequency RLC circuits Bandwidth Linear circuits Resonance Inductors Standards electronic circuits

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Domain-Specific design Abstraction with Emphasis on Neural Networks

Domain-Specific Design Abstraction with Emphasis on Neural N...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Maryam Rajabalipanah Zahra Hojati Zahra Jahanpeima Zainalabedin Navabi School of Electrical and Computer Engineering College of Engineering University of Tehran Tehran Iran

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

The increasing complexity in digital system design has introduced significant challenges, particularly in maintaining productivity relative to the rapid advancement of technology. This paper addresses the issue by presenting a new level of abstraction, termed Data Transaction Level (DTL), which operates at a higher level than the traditional Register Transfer Level (RTL). The proposed DTL design methodology draws inspiration from RTL but is tailored for the growing complexity of modern systems, particularly in neural network implementations. As neural networks are becoming essential in various applications, this paper applies the DTL methodology to hardware implementations of these networks. A SystemC-based hardware description language is introduced to facilitate the design process. The results section evaluates the effectiveness of the proposed methodology, highlighting increased productivity using the new abstraction and description language.

关键词： Productivity Industries Digital systems design methodology Neural networks Register transfer level Hardware Complexity theory Hardware design languages electronic circuits

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FPGA-Based Fault-Tolerant Speed PI Control for a Three-Phase Brushless DC Motor 16

FPGA-Based Fault-Tolerant Speed PI Control for a Three-Phase...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Ancassi, A. Minaya, J. Tarrillo, J. Universidad de Ingenieria y Tecnologia Electronic and Mechatronic Department Lima Peru

ISBN: (纸本)9798331522124

electronic devices exposed to non-ionizing radiation are susceptible to Single-Event Upsets (SEUs) in digital systems. These SEUs can lead to failures in the digital system of Brushless DC (BLDC) motor drivers, resulting in data reading errors, speed control malfunctions, phase commutation inaccuracies, and erroneous rotor position detection, which can have significant consequences in critical situations. Thus, this paper proposes to enhance the reliability of a Proportional-Integral (PI) speed control system for BLDC motors by employing the Triple Modular Redundancy (TMR) technique implemented within an FPG Artix-7. The results of the control efficiency are evaluated through its performance characteristics given through simulation and implementation. The fault tolerance validation of this proposal was carried out through fault injection campaigns. The results demonstrate that the TMR-based system can tolerate around 115% more faults than a non-TMR system, highlighting the robustness and reliability of the proposed solution. © 2025 ieee.

关键词： Brushless DC motors

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Accuracy Enhancement of Resistor-String Digital-to-Analog Converters through Averaging Dynamic Element Matching

Accuracy Enhancement of Resistor-String Digital-to-Analog Co...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Francesco Gagliardi Michele Dei Department of Information Engineering University of Pisa Pisa Italy

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In integrated Digital-to-Analog Converters (DACs), random mismatch errors among nominally equal unit elements significantly limit the achievable accuracy. This work explores the effectiveness of tailored Dynamic Element Matching (DEM) techniques in mitigating mismatch-induced non-linearity errors in resistor-string DAC architectures. Through statistical behavioural simulations, we identify effective DEM strategies that substantially reduce Integral Non-Linearity (INL). The proposed technique enables virtually zero INL errors at specific points of the transfer characteristic, which can be strategically chosen during circuit operation. Insofar, optimized design approaches for resistor-string DACs are proposed, fostering future integratedcircuit implementations with superior yield concerning accuracy and linearity specifications.

关键词： Resistors Accuracy Digital-analog conversion Linearity Integrated circuit modeling electronic circuits

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design Exploration of CMOS Building Blocks for Time-Based-Controlled DC-DC Converters Using Open-Source PDK and Tools 16

Design Exploration of CMOS Building Blocks for Time-Based-Co...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Marin, Jorge Martinez, Andres Nuncz, Andrea Rojas, Christian A. Universidad Tecnica Federico Santa Maria Department of Electronic Eng. Valparaiso Chile Advanced Center of Electrical and Electronics Engineering Universidad Técnica Federico Santa María Chile

ISBN: (纸本)9798331522124

This paper presents the design and system integration of low-power analog and digital building blocks intended for DC-DC buck converters used in IoT applications by using time-based control techniques. Each building block has been independently simulated to extract the relevant parameters for the full system. Simulation results in steady-state behaviour of the DC-DC buck converter and its system efficiency using open-source CAD tools are provided to demonstrate the effective operation of the time-based control. The maximum simulated efficiency yields 85.8 % for a conversion from 3.3 V to 1.8 V and a 270 mA load current, with a switching frequency of 1.9 MHz. The blocks have been implemented in the Skywater open-source 130-nm CMOS process, with an estimated total area of 0.27 mm2, from which the controller area represents only 4.4%. © 2025 ieee.

关键词： CMOS integrated circuits

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A Survey on Automatic Assertion Miners

A Survey on Automatic Assertion Miners

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mohammad Reza Heidari Iman Giorgio Di Natale Katell Morin-Allory CNRS Institut National Polytechnique Grenoble Alpes TIMA Univ. Grenoble Alpes Grenoble France

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In the area of functional verification, AssertionBased Verification (ABV) has gained significant attention for the advantages it provides in verifying hardware designs. This approach relies on assertions generated by automatic assertion miners. These miners employ various techniques and methods to automatically mine assertions. This paper focuses on studying the most recent, advanced, and widely used assertion miners in the field and provides an analytical comparison between them. This study aims to highlight the strengths and shortcomings of current automatic assertion miners to assist researchers and verification engineers in understanding the functionality, strengths, and limitations of each miner. By addressing these limitations, more advanced automatic assertion miners can be developed in the future.

关键词： Surveys Focusing Hardware electronic circuits

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