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A Rule-Based Approach for Minimizing Power Dissipation of Digital circuits 19

A Rule-Based Approach for Minimizing Power Dissipation of Di...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Das, Subrata Dasgupta, Parthasarathi Fiser, Petr Ghosh, Sudip Das, Dehesh Kumar Jadavpur Univ Dept Comp Sci & Engn Kolkata India Indian Inst Management Calcutta MIS Grp Kolkata India Czech Tech Univ Fac Informat Technol Prague Czech Republic IIEST Sch VLSI Technol Sibpur Howrah India

ISBN: (纸本)9781509024674

Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. The primary contributors to power dissipation in digital circuits include leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the major component. As such, an effective mechanism to minimize the power loss in such cases often involves the minimization of the switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and the results obtained are quite encouraging.

关键词： Switching activity low-power VLSI circuits CMOS power dissipation dynamic power logic optimization

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Two-level logic synthesis for low power based on new model of power dissipation

Two-level logic synthesis for low power based on new model o...

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10th ieee International Workshop on design and diagnostics of electronic circuits and systems

作者： Brzozowski, I. Kos, A. AGH Univ Sci & Technol Al Mickiewicza 30 PL-30059 Krakow Poland

ISBN: (纸本)9781424411610

Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. Therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.

关键词： CMOS integrated circuits

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Reliable Execution of Statechart-Generated Correct Embedded Software under Soft Errors 17

Reliable Execution of Statechart-Generated Correct Embedded ...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ferreira, Ronaldo R. Klotz, Thomas Voertler, Thilo da Roltl, Jean Nazar, Gabriel L. Moreira, Alvaro F. Carro, Luigi Einwich, Karsten Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil Fraunhofer Inst Integrated Circuits Dresden Germany

ISBN: (纸本)9781479945580

This paper proposes a design methodology for fault-tolerant embedded systems development that starts from software specification and goes down to hardware execution. The proposed design methodology uses formally verified and correct-by-construction software created from high-level UML statechart models for software specification and implementation. On the hardware reliability side, this paper uses the MoMa architecture for reliable embedded computing which we deploy as a soft-core onto an off-the-shelf FPGA. MoMa introduces architectural innovations that support the semantics of the UML statechart execution in a reliable fashion. The proposed design methodology is evaluated with a real automotive case study based on an exhaustive FPGA-implemented fault injection campaign.

关键词： Model-driven engineering fault-tolerance reliability soft-errors statecharts

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A Scalable Technique to Identify True Critical Paths in Sequential circuits 20

A Scalable Technique to Identify True Critical Paths in Sequ...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ubar, Raimund Kostin, Sergei Jenihhin, Maksim Raik, Jaan Tallinn Univ Technol Tallinn Estonia

ISBN: (纸本)9781538604724

The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTl) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.

关键词： timing-critical path gate-level analysis NETI

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Defect-Oriented Module-Level Fault Diagnosis in Digital circuits

Defect-Oriented Module-Level Fault Diagnosis in Digital Circ...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kostin, Sergei Ubar, Raimund Raik, Jaan Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9781424497560

We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e. g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high diagnostic resolution of the proposed approach.

关键词： digital circuits multiple faults hierarchical fault diagnosis

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A design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm 18

A Design for the 178-MHz WXGA 30-fps Optical Flow Processor ...

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Matsumura, Tetsuya Kurokawa, Aoi Imamura, Kousuke Matsuda, Yoshio Nihon Univ Coll Engn Koriyama Fukushima Japan Kanazawa Univ Coll Sci & Engn Kanazawa Ishikawa Japan

ISBN: (纸本)9781479967803

We propose an optical flow processor, which allows real-time processing of WXGA 30-fps at 178.3 MHz. By introducing the SOR method and a pipeline operation for the Gauss-Seidel method to the iterative flow calculation, computational complexity can be reduced to 14.5% when compared to the previous HOE processor. We decreased the area of the embedded memory by using the image division method, applying line memory, and optimizing the computation word length. The core size of the designed processor is 16.82 mm(2) in 90 nm process technology, which is approximately 5% of the previous HOE processor. The processor can operate completely in parallel, which ensures high-resolution scalability.

关键词： HOE optical flow processor scalability

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Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible circuits. 18

Boolean Difference Technique for Detecting All Missing Gate ...

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mondal, Joyati Mondal, Bappaditya Kole, Dipak Rahaman, Hafizur KDas, Debesh Jadavpur Univ Dept Comp Sci & Engg Kolkata 32 India Indian Inst Engn Sci & Technol Dept Comp Sci & Engg Sibpur India

ISBN: (纸本)9781479967803

Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates only. A reversible Toffoli gate has two components - the control and the target. The missing gate fault model is used for modelling defects in quantum k-CNOT gate. This work introduces Boolean Difference technique for deriving the test set for detecting all faults in a reversible circuit implemented with k-CNOT gates. Then a optimizing algorithm is used to derive optimal test set to detect all possible partial missing faults in a circuit.

关键词： Missing-gate fault quantum computing reversible logic test generation

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An Indirect Technique for Estimating Reliability of Analog and Mixed-Signal systems during Operational Life

An Indirect Technique for Estimating Reliability of Analog a...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Khan, Muhammad Aamir Kerkhoff, Hans G. Univ Twente Testable Design & Test Integrated Syst TDT Grp Ctr Telemat & Informat Technol CTIT NL-7500 AE Enschede Netherlands

ISBN: (纸本)9781467361361;9781467361354

Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

关键词： reliability input signal monitoring temperature monitoring time before failure offset voltage

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design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter 22

Design of a True Random Number Generator Based on Low Power ...

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22nd ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Derlecki, Mariusz Siwiec, Krzysztof Narczyk, Pawel Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 75 PL-00662 Warsaw Poland

ISBN: (纸本)9781728100739

This paper presents the design of an oscillator-based true random number generator. The operation of the presented TRNG architecture is based on sampling a high-frequency oscillator output with a clock generated by a low frequency noisy oscillator. The recycling folded cascode architecture was used for low power noise amplifier. A new method to achieve higher jitter in the low frequency oscillator is presented. The bit rate of the designed TRNG is 1.02 Mb/s. The circuit power consumption is 67 mu W. The results of the simulations and statistical tests of the designed random number generator arc also presented in this paper.

关键词： Cryptography Encryption Random Numbers Noise Jitter TRNG Statistical Tests

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FITTest_BENCH06:: A new set of benchmark circuits reflecting testability properties

FITTest_BENCH06:: A new set of benchmark circuits reflecting...

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Pecenka, Tomas Kotasek, Zdenek Sekanina, Lukas Brno Univ Technol Fac Informat Technol Bozetechova 2 Brno 61266 Czech Republic

ISBN: (纸本)1424401844

In the paper, the FITTest-BENCH06 set of synthetic benchmark circuits Is presented for the evaluation of diagnostic methods and tools. The structure of benchmark circuits together with their diagnostic properties is described. The set consists of 31 circuits at various levels of complexity (2 000, 10 000, 28 000, 100 000, 150 000 and 300 000 gates). Four circuits with different diagnostic properties are available for each level of circuit complexity (fault coverage is approx. 0%, 33%, 66% and 100%). The benchmark circuits are available both at the register transfer level and the gate level. In addition to the benchmark set, a method is described that was used to develop benchmark circuits with required complexity and diagnostic properties.

关键词： Circuit theory

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