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A Reliability-aware Environment for design Exploration for GPU Devices

A Reliability-aware Environment for Design Exploration for G...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Robert Limas Sierra Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

1 Nowadays, GPU platforms have gained wide importance in applications that require high processing power. Unfortunately, the advanced semiconductor technologies used for their manufacturing are prone to different types of faults. Hence, solutions are required to support the exploration of the resilience to faults of different architectures. Based on this motivation, this work presents an environment dedicated to the analysis of the impact of permanent faults on GPU platforms. This environment is based on GPGPU-Sim, with the objective of exploiting the configuration features of this tool and, thus, analyzing the effects of faults when changing the target architecture. To validate the environment and show its usability, a fault campaign has been carried out where three different GPU architectures (Kepler, Volta, and Turing) were used. In addition, each GPU has been modified with an arbitrary number of parallel processing cores (or SMs). Three representative applications (Vector Add, Scalar Product, and Matrix Multiply) were executed on each GPU, and the behavior of each architecture in the presence of permanent faults in the functional (i.e., integer unit and floating-point) units was analyzed. This fault campaign shows the usability of the environment and demonstrates its potential use to support decisions on the best architectural parameters for a given application.

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Towards No Penalty Control Hazard Handling 66

Towards No Penalty Control Hazard Handling

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Surya Balasubramanian, Linknath Rizkalla, Maher Lee, John J. Ytterdal, Trond Kumar, Mukesh Indiana University Purdue University Indianapolis Department of Electrical and Computer Engineering Indianapolis United States Norwegian University of Science and Technology Department of Electronic Systems Trondheim Norway Indian Institute of Technology Indore Department of Electrical Engineering Indore India

ISBN: (纸本)9798350302103

Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a novel mechanism that makes microcontrollers forgo branch predictors and thereby eliminate branch mispredictions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The proposed technique is implemented as five different modules that work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed system was tested using test-bench with modifications to make the test-code compatible with the designed architecture. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles. Moreover, the latency of instruction fetch stage of pipeline integrated with the proposed architecture is 330 ps (3 GHz approx.) which is more than the operating frequencies of microcontrollers. Therefore, the proposed design can be integrated in high performance microcontrollers. © 2023 ieee.

关键词： branch predictor control transfer instruction in-order five stage pipeline microcontroller mispredictions

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Dynamic MAC Unit Pruning Techniques in Runtime RTL Simulation for Area-Accuracy Efficient Implementation of Neural Network Accelerator 66

Dynamic MAC Unit Pruning Techniques in Runtime RTL Simulatio...

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Kwon, Jisu Yun, Heuijee Park, Daejin School of Electronic and Electrical Engineering Kyungpook National University Daegu41566 Korea Republic of

ISBN: (纸本)9798350302103

designing lightweight hardware accelerators that maintain model inference accuracy is a challenging task in edge artificial intelligence (AI) because of the heterogeneous design requirements between the software model and hardware accelerator. While model pruning is an effective approach for reducing the number of parameters and computational requirements, conventional software model pruning leads to inefficient overhead when deploying the model in a general-purpose accelerator for inference. To overcome these challenges, we propose an empirical register transfer level (RTL) simulation-based accelerator pruning technique that is optimized for domain applications and models. Specifically, the proposed technique measures the dynamic switching of processing element (PE) unit-wise signals during dataset sample inference on a 2D array of PEs and replaces it with dummy PEs based on the RTL simulation results. The proposed approach reduces the accelerator's area and power resource consumption while maintaining baseline accuracy. We automated the RTL generation and simulation reconfiguration process to enable PE pruning that requires iterative and empirical RTL simulation based on signal switching count results. Our experimental results show that while the model's inference accuracy decreased by only 1% (98% to 97%), we were able to reduce dynamic signal switching and synthesized area by up to 9.78% and 4.25%, respectively. Our approach suggests a lightweight hardware accelerator design that is dedicated to the target application and can be scaled without modifying the model. © 2023 ieee.

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ReFACE: Efficient design Methodology for Acceleration of Digital Filter Implementations 23

ReFACE: Efficient Design Methodology for Acceleration of Dig...

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23rd International symposium on Quality electronic design (ISQED)

作者： Roohi, Arman Angizi, Shaahin Navaeilavasani, Pooriya Taheri, MohammadReza Univ Nebraska Lincoln Sch Comp Lincoln NE 68588 USA New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ USA

ISBN: (纸本)9781665494663

Because of the impressive performance and success of artificial intelligence (AI)-based applications, filters as a primary part of digital signal processing systems are widely used, especially finite impulse response (FIR) filtering. Although they offer several advantages, such as stability, they are computationally intensive. Hence, in this paper, we propose a systematic methodology to efficiently implement computing in-memory (CIM) accelerators for FIR filters using various CMOS and post-CMOS technologies, referred to as ReFACE. ReFACE leverages a residue number system (RNS) to speed up the essential operations of digital filters, instead of traditional arithmetic implementation that suffers from the inevitable lengthy carry propagation chain. Moreover, the CIM architecture eliminates the off-chip data transfer by leveraging the maximum internal bandwidth of memory chips to realize a local and parallel computation on small residues independently. Taking advantage of both RNS and CIM results in significant power and latency reduction. As a proof-of-concept, ReFACE is leveraged to implement a 4-tap RNS FIR. The simulation results verified its superior performance with up to 85 x and 12x improvement in energy consumption and execution time, respectively, compared with an ASIC accelerator.

关键词： Computing in-memory finite impulse response filter residue-number system beyond CMOS technologies

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design and application of error-compensated approximate multipliers 4

Design and application of error-compensated approximate mult...

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4th International symposium on Artificial Intelligence and Intelligent Manufacturing, AIIM 2024

作者： Tan, Yuchi Zhao, Zhao Huang, Xiaobing Wu, Xinchun School of Information Science and Technology Southwest Jiaotong University Chengdu China Technology Co. Ltd Chengdu China School of Integrated Circuits Science and Engineering Southwest Jiaotong University Chengdu China

ISBN: (纸本)9798331541729

In the context of the rapid development of electronic information technology, the rapid progress of emerging technologies such as the Internet of Things, big data analysis and artificial intelligence has posed unprecedented performance and power consumption challenges to computing systems. In many compute-intensive applications, completely accurate calculations are not always necessary. These applications tend to tolerate a certain level of calculation error. Therefore, it is a very effective idea to use approximate calculations and introduce errors in exchange for performance and power optimization. This thesis focuses on the study of approximate Booth multipliers and proposes a new approximate multiplier structure Approximate Error-compensated Booth Multipliers (AEBM), designed with error compensation. This includes an approximate Booth encoder, a newly proposed approximate 3-2 compressor and 4-2 compressor, and an approximate partial product array with error compensation based on the division of approximate factors. Compared to the structure discussed in [1], the key hardware performance indicator PDP of the AEBM structure is only 50.3%, and NMED is only 53.4%. Compared to [2], the PDP of the AEBM structure is 94%, and NMED is 1.4%, achieving a comprehensive design of accuracy and hardware performance. Finally, when applied to a neural network for image denoising, AEBM outperforms other approximate multipliers in terms of PSNR and SSIM. Compared with the exact multiplier, PSNR only loses 0.4, SSIM only loses 0.0158. © 2024 ieee.

关键词： approximate Booth multiplier approximate computing Error compensation image denoising

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MLSBench: A Benchmark Set for Machine Learning based FPGA HLS design Flows 13

MLSBench: A Benchmark Set for Machine Learning based FPGA HL...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Goswami, Pingakshya Shahshahani, Masoud Bhatia, Dinesh Univ Texas Dallas Dept Elect Engn Richardson TX 75080 USA

ISBN: (纸本)9781665420082

High-Level Synthesis (HLS) is becoming a defacto standard for starting large FPGA-based design projects. FPGA design flows are completely embracing HLS based methodologies so that software engineers with almost no hardware design skills can easily use their tools. Behavioral descriptions used during the high-level synthesis (HLS) are completely technology-independent, making it hard for designers to interpret how changes in the synthesis options affect the resultant circuit. Researchers across industry and academia are performing research in the field of machine-learning-based predictive high-level synthesis (HLS) tool design, where the quality of results (QOR) can be predicted using various ML techniques. One of the greatest challenges in all these works is the availability of open-source HLS designs on which the designers can train and predict their models. Generation of benchmarks is a time-consuming process and lack of availability of standard benchmarks prevents fair comparison among various proposed models. In this paper, we propose a methodology for generating diverse designs with various variations from a single design. We have created a data-set of more than 6000 synthesizable FPGA HLS designs written in C/C++ and System C. We provide a detailed statistical analysis of the generated benchmarks. The data set is available for public use. We have demonstrated the use of our data-set in case studies that involve quick model-based design space exploration.

关键词： High Level Synthesis Machine Learning Benchmarks Datasets

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VLSI Architecture design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application 13

VLSI Architecture Design Methodology for Deep learning based...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Nimbekar, Anagha Dinesh, Y. V. Sai Gautam, Arvind Hunsigida, Vidhumouli Nali, Appa Rao Acharyya, Amit IIT Hyderabad Dept Elect Engn Hyderabad 502285 Telangana India Xilinx Madhapur India

ISBN: (纸本)9781665420082

Recently, many works have proposed an highly accurate deep learning based movement classification algorithms for the assistive technology applications. But very less importance is given for it's corresponding hardward implementation. In this paper we proposed an VLSI architecture design methodology for deep learning based movement classification for assistive technology applications. LoCoMo-Net and MyoNet are the two Deep learning based networks proposed by Gautam et al [1] [2] for upper limb and lower limb for assistive technology. The proposed architecture is capable enough to adapt both the networks. We have implemented the architecture on ZYNQ ultra-scale + MPSoC zcu102 FPGA. LoCoMo-Net consumes 3.5 Watts of on chip power and MyoNet consumes 5 Watts of on chip power on the FPGA. LoCoMo-Net takes 1.876ms of time to classify the task and MyoNet takes 61.988ms of time to classify the task on FPGA.

关键词： Convolutional Neural Network (CNN) Long Short Term Memory (LSTM) LoCoMO-Net MyoNet sEMG movement classification

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Machine Learning based Surrogate Modeling for Wave Impedances in Rectangular Dielectric Waveguides

Machine Learning based Surrogate Modeling for Wave Impedance...

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2023 ieee/MTT-S International Microwave symposium, IMS 2023

作者： Schmitz, Robin Hattenhorst, Birk Baer, Christoph Musch, Thomas Rolfes, Ilona Ruhr University Institute of Microwave Systems Bochum Germany Ruhr University Institute of Electronic Circuits Bochum Germany

ISBN: (纸本)9798350347647

Even though the behavior of rectangular dielectric waveguides (RDWGs) can be evaluated accurately using numerical simulations, limited time and computational resources generally do not allow an extensive exploration of the design space. Thus, in this paper we present a way to develop a fast-to-evaluate surrogate model for the wave impedance of the fundamental mode HE11 in RDWGs at frequencies between 134 and 141 GHz. To this end, gaussian process regression (GPR) with a customized covariance function as well as artificial neural networks (ANNs) and polynomial regression (PR) are applied. Compared by the mean absolute deviation (MAD), our finally proposed model shows much better agreement with numerical solutions than Maractili's famous approximate analytical approach (MA). In contrast to MA, our approach is furthermore applicable to DWGs with arbitrary cross-sections. © 2023 ieee.

关键词： Neural networks

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Fault Tolerance in Stochastic circuits for Recurrent Sequential Neural Networks 33

Fault Tolerance in Stochastic Circuits for Recurrent Sequent...

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33rd ieee Asian Test symposium, ATS 2024

作者： Sengupta, Roshwin Polian, Ilia Hayes, John P. University of Stuttgart Institute of Computer Architecture and Computer Engineering Stuttgart Germany University of Michigan Computer Engineering Laboratory Ann ArborMI United States

ISBN: (纸本)9798331529161

Stochastic computing (SC) provides low-area, power-efficient hardware solutions suitable for edge systems, but its scalability poses challenges due to its precision limitations, especially in noisy environments. This paper investigates the fault tolerance of key SC components, such as stochastic number generators (SNGs) and activation functions (AFs), within recurrent and sequential networks like long short-term memory (LSTM) networks. We inject bit-flip faults into a network's most sensitive inputs, weights and AFs, and study fault propagation across different network layers. Our findings reveal that SC component choices significantly influence fault tolerance. For example, networks using Sobol-based SNGs with tanh AFs exhibited stronger resilience than those with LFSR-based SNGs and ReLU AFs, by maintaining higher accuracy under fault conditions. However, the accuracy of the networks declined significantly under simultaneous faults in inputs, weights and AFs. Additionally, while increasing stochastic number lengths improved fault tolerance, they also increased latency. Nevertheless, the SC networks achieved up to 54% area and 72% power savings, making them ideal for resource-constrained applications. We also found that there is a trade-off between efficiency and fault tolerance: SC designs that focus on resource efficiency may struggle in noisy environments, where fault-tolerant SC designs are more effective. This implies that fault resilience in SC architectures depend heavily on design choices and cannot be assumed inherent across all configurations. © 2024 ieee.

关键词： Long short-term memory

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35th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design, SBCCI 2022 - Proceedings

35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits a...

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35th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design, SBCCI 2022

ISBN: (纸本)9781665481281

The proceedings contain 47 papers. The topics discussed include: deep neural network feasibility using analog spiking neurons;improving soft error robustness of full adder circuits with decoupling cell and transistor sizing;a 0.55-V oscillator with improved stability against temperature and supply-voltage variations;comparative analysis of hardware implementations of a convolutional neural network;circuit reliability analysis with considerations of aging effect;deep neural network feasibility using analog spiking neurons;exploring machine learning for electrical behavior prediction: the CMOS inverter case study;conversion time-power tradeoff in capacitance-to-digital converters with dual-mode logic;low noise broadband amplifier for breast cancer system;an all-digital programmable current-limited discharge circuitry for a safe electrical stimulation;miniaturized sign-magnitude stochastic-binary FIR filter architecture with enhanced accuracy;energy-efficient forwarding routing algorithm with bidirectional link quality estimator for wireless sensor networks;and a custom interconnection multi-FPGA framework for distributed processing applications.

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