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共 4789 条记录，以下是211-220 订阅

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A Build-In Self-Test Technique for RF Mixers

A Build-In Self-Test Technique for RF Mixers

引用

13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Dermentzoglou, Lambros Arapoyanni, Angela Tsiatouhas, Yiorgos Univ Athens Dept Informat & Telecommun Athens Greece Univ Ioannina Dept Comp Sci Ioannina Greece

ISBN: (纸本)9781424466139

A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. This is a defect-oriented test scheme that dynamically sets the Mixer to operate in homodyne mode. The DC level generated at its output is used to control the oscillation frequency of a simple voltage controlled oscillator. Deviations of the oscillation frequency from the expected range of values indicate a defective Mixer. The proposed BiST technique has been applied to a typical receiver's differential RF Mixer using a 0.35 mu m CMOS technology. Simulation results validated the efficiency of the BiST circuit which was capable to provide a high fault coverage of catastrophic faults (which exceeds 91%) and a small test application time (1 mu s), at a silicon area cost approximately 16% of the Mixer area.

关键词： Build-in-Self Test design for Testability RF Mixer Defect Based Testing

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Fast Just-In-Time Translated Simulator for ASIP design

Fast Just-In-Time Translated Simulator for ASIP Design

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Prikryl, Zdenek Kroustek, Jakub Hruska, Tomas Kolar, Dusan Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781424497560

The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.

关键词： architecture description languages simulation testing application-specific instruction set processors

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A Methodology to Verify Digital IP's Within Mixed-Signal systems 21

A Methodology to Verify Digital IP's Within Mixed-Signal Sys...

引用

21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Navaneetha, C. M. Breitenreiter, Anselm Ulbricht, Markus Krstic, Milos IHP Syst Design Technol Pk 25 D-15236 Frankfurt Oder Germany Univ Potsdam D-14469 Potsdam Germany

ISBN: (纸本)9781538657546

This paper describes a methodology to improve the quality of verification and an approach to dimension the arithmetic of register transfer level (RTL) model of the digital part of the mixed-signal system. This includes the refinement of the high level model of the system and generation of a MATLAB fixed-point model and test-bench for MATLAB-HDL co-simulation. Additionally an approach for the dimensioning of an adaptive equalizer in frequency domain is discussed. The proposed methodology and results of analysis are applied to verify 10BASE-T/100BASE-TX Ethernet PHY IP.

关键词： 10BASE-T/100BASE-TX Ethernet PHY fixed-point model co-simulation quantization effects system verification methodology test-bench

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Structure-Preserving Modeling of Safety-Critical Combinational circuits 20

Structure-Preserving Modeling of Safety-Critical Combination...

引用

20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rasim, Feim Ridvan Kocar, Canan Sattler, Sebastian M. Friedrich Alexander Univ Erlangen Nuremberg Chair Reliable Circuits & Syst Paul Gordan Str 5 D-91052 Erlangen Germany

ISBN: (纸本)9781538604724

In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph. For creating a signal flow plan it is necessary to swap the nodes and the edges in the signal flow graph. After executing this action the result is a signal flow plan. A value table exhibits the coding of the whole circuit. Then the so called module view is used to get the familiar compact display and neighborhood relations are repeated once more, the resolution method is used. It is observed that in digital circuits, undefined results can occur but these must be avoided in safety critical circuits. These events have to be secured in practice by costly and expensive verification and testing. In order to deal with the problem now, the structure preserving modeling has to be understood, since this is the only way to achieve a one-purpose, qualitative and cost effective search for errors.

关键词： Combinational circuit structure modeling symbolic analysis signal flow graph Boolean function

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VARMA-VARiability Modelling and Analysis Tool

VARMA-VARiability Modelling and Analysis Tool

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Russell, G. Burns, F. Yakovlev, A. Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

ISBN: (纸本)9781467311854

Process parameter variability in IC manufacturing has become an increasingly important issue as feature scaling descends further into the deep submicron region. Within industry the development of EDA tools associated with 'process-aware-design' has a high priority as the impact on circuit performance due to process variations is having increasingly adverse effects on yield and performance. VARMA is a variability analysis tool which enables optimisation of both manufacturing process and nano-electronic circuit design in order to avoid 'manufacturing surprises' resulting in costly chip respins, delays in reaching the market place and the subsequent loss of profitability.

关键词： VLSI design process variability CAD tools

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LC-VCO design Automation Tool for Nanometer CMOS Technology

LC-VCO Design Automation Tool for Nanometer CMOS Technology

引用

ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Siwiec, Krzysztof Borejko, Tomasz Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland

ISBN: (纸本)9781467311854

In this paper a low-voltage LC voltage-controlled oscillator (VCO) design automation tool has been presented. The tool is based on design methodology, which takes under consideration trade-offs between power consumption, phase noise and tuning range. NMOS only architecture is considered because of its capability to work with low supply voltages. One of the goals, while creating the tool, was to make it technology independent. This was achieved by creating SKILL scripts that allows fast configuration of design library for specified technology. Trade-offs between power consumption, phase noise and tuning range are analyzed and based on them design flow has been proposed. Finally two design examples in 90 and 130 nm CMOS technology have been presented.

关键词： CMOS technology tuning range Computer-Aided design Phase noise Nanometers Power consumption

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Energy-Aware Software Development for Embedded systems in HW/SW Co-design

Energy-Aware Software Development for Embedded Systems in HW...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ehrlich, Paul Radke, Stephan Fraunhofer IIS Design Automat Div EAS Dresden Germany

ISBN: (纸本)9781467361361;9781467361354

Power constrains are becoming increasingly important for embedded systems, especially when considering mobile applications. These systems are characterized by the presence of a dedicated processor running application-specific software. Current approaches only focus on power optimization in one design domain, such as the hardware or the software one. However, to meet the tight power constrains, both have to be investigated in relation. This paper proposes a novel approach to support the software developing process which takes this relation into account. Based on hardware/software co-simulation, the power consumption of the hardware is annotated to the corresponding source code. Hence, the consumption of the system is directly visible during software refinements of the microcontroller. After each refinement cycle, an overall power optimization can be accomplished. The approach is applied to an example system which comprises the embedded software of a MSP430 microcontroller and its controlled external peripherals. Using the example, the potential of the approach is discussed. Moreover, the power annotation process is defined and the data exchange formats are specified. Therefore, the approach is also applicable to any other controller type.

关键词： Power-Analysis Embedded systems design Hardware/Software Co-design Power System Simulation

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Parity Waterfall Method 19

Parity Waterfall Method

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Borecky, Jaroslav Kohlik, Martin Kubatova, Hana Czech Tech Univ Dept Digital Design Fac Informat Technol Tech 9 Prague Czech Republic

ISBN: (纸本)9781509024674

This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. The utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. The method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. The experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). These results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.

关键词： Field programmable gate arrays (FPGA)

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SiP design Flow and 3D DRC for MEMS 17

SiP Design Flow and 3D DRC for MEMS

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mehdaoui, A. Pagazani, J. Schroepfer, G. Lissorgues, G. Coventor SARL Villebon Sur Yvette France Univ Paris Est ESYCOM UPEMLV ESIEE Paris Paris France

ISBN: (纸本)9781479945580

he contribution will describe in detail recent development related to the integration of MEMS into a SiP design flow. A key step in implementing system-level simulation is the translation of the physical behavior of the constitutive components in a system from the more fine-grained continuum level to more abstract, coarse grained models. An important challenge is the preservation of accuracy from fine-grained simulation to a degree that is deemed adequate. In order for the simulator to run in a reasonable time, the system-level model should only include the degrees of freedom (DOF) necessary to capture the relevant physics. Very handy in this sense are methods of model-order reduction (MOR), which under certain conditions enable almost automatic transfer from the continuum level simulation up to the behavioral models with minimal loss of accuracy.

关键词： Microelectromechanical systems design flow Motor Activity behavioral models simulator optical coherence tomography angiography device system parameter Continuum simulating CONSERVATION

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New current monitor using auto zero voltage comparator for I_DD testing of mixed-signal circuits

New current monitor using auto zero voltage comparator for I...

引用

9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Nagy, Vladislav Stopjakova, Viera Slovak Univ Technol Bratislava Dept Microelect Ilkovicova 3 Bratislava 81219 Slovakia

ISBN: (纸本)1424401844

An approach to the dynamic supply current sensing based on the measurement of voltage drop across a parasitic resistance of the supply voltage metal routing is presented. Auto-zero technique for voltage comparator offset cancellation, which provides very accurate and sensitive low voltage drop measurement is proposed. Therefore, one may use the proposed sensor as a current monitor for dynamic current testing of mixed-signal circuits without any additional element necessarily connected in series with the power supply line. The proposed current monitor was designed in a 0.35 mu m CMOS technology.

关键词： Comparator circuits

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