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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"
4789 条 记 录,以下是211-220 订阅
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A Build-In Self-Test Technique for RF Mixers
A Build-In Self-Test Technique for RF Mixers
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13th ieee symposium on design and diagnostics of electronic circuits and systems
作者: Dermentzoglou, Lambros Arapoyanni, Angela Tsiatouhas, Yiorgos Univ Athens Dept Informat & Telecommun Athens Greece Univ Ioannina Dept Comp Sci Ioannina Greece
A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. This is a defect-oriented test scheme that dynamically sets the Mixer to operate in homody... 详细信息
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Fast Just-In-Time Translated Simulator for ASIP design
Fast Just-In-Time Translated Simulator for ASIP Design
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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Prikryl, Zdenek Kroustek, Jakub Hruska, Tomas Kolar, Dusan Brno Univ Technol Fac Informat Technol Brno Czech Republic
The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic... 详细信息
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A Methodology to Verify Digital IP's Within Mixed-Signal systems  21
A Methodology to Verify Digital IP's Within Mixed-Signal Sys...
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21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Navaneetha, C. M. Breitenreiter, Anselm Ulbricht, Markus Krstic, Milos IHP Syst Design Technol Pk 25 D-15236 Frankfurt Oder Germany Univ Potsdam D-14469 Potsdam Germany
This paper describes a methodology to improve the quality of verification and an approach to dimension the arithmetic of register transfer level (RTL) model of the digital part of the mixed-signal system. This include... 详细信息
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Structure-Preserving Modeling of Safety-Critical Combinational circuits  20
Structure-Preserving Modeling of Safety-Critical Combination...
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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Rasim, Feim Ridvan Kocar, Canan Sattler, Sebastian M. Friedrich Alexander Univ Erlangen Nuremberg Chair Reliable Circuits & Syst Paul Gordan Str 5 D-91052 Erlangen Germany
In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph. For creating a signal flow plan it ... 详细信息
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VARMA-VARiability Modelling and Analysis Tool
VARMA-VARiability Modelling and Analysis Tool
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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Russell, G. Burns, F. Yakovlev, A. Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England
Process parameter variability in IC manufacturing has become an increasingly important issue as feature scaling descends further into the deep submicron region. Within industry the development of EDA tools associated ... 详细信息
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LC-VCO design Automation Tool for Nanometer CMOS Technology
LC-VCO Design Automation Tool for Nanometer CMOS Technology
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ieee 15th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Siwiec, Krzysztof Borejko, Tomasz Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland
In this paper a low-voltage LC voltage-controlled oscillator (VCO) design automation tool has been presented. The tool is based on design methodology, which takes under consideration trade-offs between power consumpti... 详细信息
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Energy-Aware Software Development for Embedded systems in HW/SW Co-design
Energy-Aware Software Development for Embedded Systems in HW...
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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Ehrlich, Paul Radke, Stephan Fraunhofer IIS Design Automat Div EAS Dresden Germany
Power constrains are becoming increasingly important for embedded systems, especially when considering mobile applications. These systems are characterized by the presence of a dedicated processor running application-... 详细信息
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Parity Waterfall Method  19
Parity Waterfall Method
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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)
作者: Borecky, Jaroslav Kohlik, Martin Kubatova, Hana Czech Tech Univ Dept Digital Design Fac Informat Technol Tech 9 Prague Czech Republic
This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of a... 详细信息
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SiP design Flow and 3D DRC for MEMS  17
SiP Design Flow and 3D DRC for MEMS
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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)
作者: Mehdaoui, A. Pagazani, J. Schroepfer, G. Lissorgues, G. Coventor SARL Villebon Sur Yvette France Univ Paris Est ESYCOM UPEMLV ESIEE Paris Paris France
he contribution will describe in detail recent development related to the integration of MEMS into a SiP design flow. A key step in implementing system-level simulation is the translation of the physical behavior of t... 详细信息
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New current monitor using auto zero voltage comparator for IDD testing of mixed-signal circuits
New current monitor using auto zero voltage comparator for I...
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9th ieee Workshop on design and diagnostics of electronic circuits and systems
作者: Nagy, Vladislav Stopjakova, Viera Slovak Univ Technol Bratislava Dept Microelect Ilkovicova 3 Bratislava 81219 Slovakia
An approach to the dynamic supply current sensing based on the measurement of voltage drop across a parasitic resistance of the supply voltage metal routing is presented. Auto-zero technique for voltage comparator off... 详细信息
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