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Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate design 13

Calibration of Logical Effort Transistor Sizing for On-the-F...

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13th Latin America symposium on circuits and System (LASCAS)

作者： Kessler, Henrique Bohlke, Murilo da Rosa Jr, Leomar S. Porto, Marcelo Camargo, Vinicius V. Fed Univ Pelotas UFPel Postgrad Program Comp PPGC Pelotas RS Brazil Fed Univ Pelotas UFPel Ctr Technol Dev CDTec Pelotas RS Brazil

ISBN: (纸本)9781665420082

Gate sizing has been widely studied to improve power dissipation and performance characteristics in VLSI design. Recent developments allow the automatic design of static CMOS complex gates for a reduction in power dissipation. It is possible to observe a lack of different transistor sizing in these works using minimum transistor dimension or the Logical Effort technique. In this work, we propose a methodology to adapt the Logical Effort technique for low-power applications. Results show significant improvements on up to 99.9% of the studied cases in power-performance trade-off across multiple simulation environments for a 45nm CMOS technology.

关键词： Cell design automation static CMOS complex gate gate sizing transistor network

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DeepTune: robust global optimization of electronic circuit design via neuro-symbolic optimization 53

DeepTune: robust global optimization of electronic circuit d...

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ieee International symposium on circuits and systems (ieee ISCAS)

作者： Wu, Chai Wah Wu, Ann Chen Strom, James IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA IBM Syst Grp Poughkeepsie NY 12601 USA IBM Syst Grp Rochester MN 55901 USA

ISBN: (纸本)9781728192017

We present an application of machine learning to automated robust optimization of electronic circuit design that combines artificial neural networks and global optimization. A neural network regressor is constructed to predict circuit operation metrics such as power, offset, delay, phase margin based on input parameters such as device size, temperature, supply voltage and current, and process corner. This regressor is then used to build an objective function for global optimization to find the optimal set of controllable parameters that optimize the objective function subject to input constraints such as device size range and output constraints such as power consumption or delay. Experimental results from tuning state-of-the-art high performance PLL circuits show that this framework is promising and can in much less time find optimized circuits that outperform circuit designs that were manually tuned by a skilled circuit designer.

关键词： neural networks machine intelligence solid state circuit design analog integrated circuits design automation

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Improved Approximate Multipliers for Single-Precision Floating-Point Hardware design 13

Improved Approximate Multipliers for Single-Precision Floati...

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13th Latin America symposium on circuits and System (LASCAS)

作者： da Costa, Patricia Pereira, Pedro T. L. Abreu, Brunno A. Paim, Guilherme da Costa, Eduardo Bampi, Sergio Fed Univ Rio Grande do Sul UFRGS Grad Program Microelect PGMicro Porto Alegre RS Brazil Catholic Univ Pelotas UCPel Grad Program Elect Engn & Comp Pelotas RS Brazil

ISBN: (纸本)9781665420082

This paper reveals that state-of-the-art integer approximate multipliers (AxMs) present dispensable blocks when specifically embedded within a floating-point (FP) architecture. This paper proposes and implements arithmetic simplifications that significantly improve four state-of-the-art AxMs for FP. The results for 32-bit FP (FP-32) show that our improved 24-bit integer AxMs (i.e., specific for FP) reduce area from about 4.2x up to 12.9x in four different AxMs when compared with the original 24-bit AxM generic integer multiplier. We also perform an AxC design space exploration (DSE) of FP-32 Least Mean Squares Adaptive Filters (LMS-AF) architectures employing the four improved AxM proposals. We present quality-energy and -area DSE trade-offs in an approximate FP-32 LMS-AF kernel, in terms of Pareto fronts, showing that we can still maintain a fully functional harmonics elimination. Pareto front total energy reduction ranges from 43.4% (1.27x) to 70.3% (3.37x) w.r.t. the precise multiplier.

关键词： Approximate Multipliers Floating-Point LMS

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EMI and EMC in electronics Course at the FTS, University of Novi Sad 22

EMI and EMC in Electronics Course at the FTS, University of ...

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22nd International symposium on Power electronics, Ee 2023

作者： Damnjanovic, Mirjana Babkovic, Kalman Kisic, Milica University of Novi Sad Electronic and Telecommunication Engineering Faculty of Technical Sciences Dept. of Power Novi Sad Serbia

ISBN: (纸本)9798350343175

In the Master Academic Studies of Power, electronics and Telecommunication Engineering, at the Faculty of Technical Sciences, University of Novi Sad, Electromagnetic Interference and Electromagnetic Compatibility in electronics is a subject students can choose. Within this course, students gain theoretical and practical knowledge in this field. The most economical way of reducing electromagnetic interference (EMI) is to use appropriate methods during the system design phase. In this course the students learn to design electronic circuits and systems immune to EMI, to implement, test, and apply EMI protection components (such as ferrite EMI suppressors, varistors, etc.), to design good PCB layouts, and use proper grounding and shielding to meet EMC standards (electromagnetic compatibility standards). In this paper, the structure of the course is presented. Additionally, a few examples are shown of the simulation tasks and laboratory exercises, giving an insight into the laboratory equipment used for the course. © 2023 ieee.

关键词： Signal interference

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2022 ieee 13th Latin American symposium on circuits and systems, LASCAS 2022

2022 IEEE 13th Latin American Symposium on Circuits and Syst...

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13th ieee Latin American symposium on circuits and systems, LASCAS 2022

ISBN: (纸本)9781665420082

The proceedings contain 50 papers. The topics discussed include: evaluating a machine learning-based approach for cache configuration;22nm CMOS pW standby power flip-flops with/without security using dynamic leakage suppression logic;ultra-low-power CMOS voltage reference topologies regarding technology node;on the netlist gate-level pruning for tree-based machine learning accelerators;a novel single lead to 12-lead ECG reconstruction methodology using convolutional neural networks and LSTM;hybrid comparator and window switching scheme for low-power SAR ADC;a fast approximate function generation method to ATMR architecture;and a highly compact 1W Ku-band power amplifier.

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A Planar Coil design Using Deep Learning 66

A Planar Coil Design Using Deep Learning

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2023 ieee 66th International Midwest symposium on circuits and systems, MWSCAS 2023

作者： Nezaratizadeh, Ali Mahmud, Sultan Khalifa, Adam University of Florida Electrical and Computer Engineering Department GainesvilleFL United States

ISBN: (纸本)9798350302103

designing a coil for wireless power transfer involves considering various factors, such as geometry, quality factor, and self-resonance frequency. While there are theoretical approaches, designers face numerous challenges due to the interdependence and trade-offs among these factors. Additionally, the electromagnetic simulation of coils is a time-consuming process, particularly when dealing with intricate details. In this paper, we present an algorithm that addresses these challenges by generating coil images corresponding to desired properties, as represented by the S11(reflection coefficient), which encompasses coil self-resonance frequency (SRF), impedances, and quality factors. The proposed algorithm has two deep learning networks for creating electromagnetic coil structures from electronic circuit S11diagrams. The first network is a conditional Deep Convolutional Generative Adversarial Network (cDCGAN) that uses coil images and their corresponding S11diagrams as its dataset. This network can generate an image of the coil structure from an input S11diagram. The second network reconstructs S11diagrams for the first network based on the optimized coil model S11result. The dataset of the second network is composed of the labels of the first network (coil S11diagrams). Upon completion of the training process, the deep learning network generates a novel coil image based on the input S-parameter diagram, which is tailored to fulfill the desired coil properties. © 2023 ieee.

关键词： cDCGAN Coil Deep Learning Wireless Power Transfer

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Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell design 28

Innovative Circuit Level Methodology for FinFET based Low-Po...

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28th International symposium on VLSI design and Test, VDAT 2024

作者： Gupta, Vishal Sribhuvaneshwari, H. Das, Tanmaya Kumar Khandelwal, Saurabh Akashe, Shyam Vellore Institute of Technology School of Electronics Engineering Tamil Nadu Vellore India Sri Shakthi Institute of Engineering and Technology Dept. of Electronics and Communication Engineering Tamil Nadu Coimbatore India Oxford Brookes University School of Ecm Oxford United Kingdom Itm University Dept. of Electronics & Communication Engineering Madhya Pradesh Gwalior India

ISBN: (纸本)9798350380101

Nowadays, minimizing static power dissipation is a critical challenge in electronic systems as technology is moving into the nanoscale regime. Semiconductor devices are greatly affected by the short-channel effects and other process and parametric variations. A novel and comprehensive circuit-level technique is needed to maintain a sufficient manufacturing yield while balancing area, robustness, and power. A substitute for bulk devices in static random-access memory (SRAM) design is the FinFET (fin-field effect transistor) device-based design. Based on the literature, multiple techniques have been explored in previous years to reduce static power dissipation. Still, they have only successfully reduced a small percentage of static power. In this work, we developed a hybrid approach for designing six transistors (6T)-based SRAM cell using FinFET technology. The projected approach significantly reduces the amount of leakage current and leakage power in standby mode without any additional area cost. We achieved reductions of 26% and 32% approx., respectively, in the analysis of leakage current and static power dissipation as compared to the ordinary 6T SRAM design based on the FinFET technology. The simulation is performed in the cadence virtuoso environment at a 45 nm technology node. Since the FinFET device lowers static power dissipation by minimizing short-channel effects, it is a desirable semiconductor technology for designing nanoscale memory circuits in the future. © 2024 ieee.

关键词： FinFET

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A Novel 2:1 Multiplexer Based Quaternary Full Adder 8

A Novel 2:1 Multiplexer Based Quaternary Full Adder

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8th ieee International symposium on Smart electronic systems, iSES 2022

作者： Musala, Sarada Vasavi, P. Durga Spandana, B. Srinivasulu, Avireni Ravariu, Cristian Vignan's Foundation for Science Technology and Research Electronics and Communication Engineering A.P. Vadlamudi522213 India Mohanbabu University Electronics and Communication Engineering A.P. Tirupathi India Department of Electronic Devices Circuits and Architectures Polytechnic University of Bucharest UPB Romania

ISBN: (纸本)9798350399226

Researchers are looking into various post-silicon and post-binary logic solutions to address the problems brought on by expanding silicon transistors. Building Quaternary Logic circuits using Carbon Nanotube Field Effect Transistors (CNTFETs) is one such solution. Since they can be utilized to achieve a range of threshold voltages by altering their physical dimensions, CNTFETs are an excellent choice for Quaternary logic circuit implementation. This work introduces a brand-new 2:1 Multiplexer-based Quaternary Full Adder. The Quaternary Full Adder in this design is built with a 2:1 multiplexer-based design approach. Therefore, compared to conventional designs, fewer transistors are needed. Comparing suggested Full Adder modules to current one's reveals that the 2:1 multiplexer-based method leads in lower power usage. A variety of operating situations, including power, delay, and power delay product, have been made the transition by these proposed devices. © 2022 ieee.

关键词： Carbon nanotube field effect transistors

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design of CNTFET based Ternary Subtractor using Unary Operators 8

Design of CNTFET based Ternary Subtractor using Unary Operat...

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8th ieee International symposium on Smart electronic systems, iSES 2022

作者： Musala, Sarada Valluri, Aswini Gurubrahmam, P. Meghana, G. Yashoda, N. Dept. of ECE Vignan's Foundation for Science Technology and Research Deemed to Be University Vadlamudi522213 India

ISBN: (纸本)9798350399226

The Ternary logic, a Multiple-valued Logic(MVL), which is an alternative approach of the conventional Binary logic has gained the attention of VLSI designers because of its advantages of higher operating speeds, lesser chip area and reduced interconnects. The principal aim of Multi-threshold design can be achieved by using of Carbon Nanotube Field Effect Transistors (CNTFETs) by incorporating the scalable threshold voltages of it. The article proposes a CNTFET deployed Ternary Half Subtractor and Full Subtractor with improved Energy consumption. The paper also uses Unary operators for improving its performance. Simulations are done in CNTFET 32nm technology at 900mv for realizing the performance metric of the circuits in the terms of Energy consumption. © 2022 ieee.

关键词： Carbon nanotube field effect transistors

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Development of a Baseband Amplifier for a 130 nm CMOS process using open-source design flow 6

Development of a Baseband Amplifier for a 130 nm CMOS proces...

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6th International symposium on Instrumentation systems, circuits and Transducers, INSCIT 2022

作者： Oliveira, Wisla M. M. Brito-Filho, Francisco A. Engineering and Technology Department Mossoro Brazil

ISBN: (数字)9781665471688

ISBN: (纸本)9781665471688

This paper addresses an analog-Type integrated circuit development using open-source tools and process design kit. The SkyWater 130 nanometer CMOS process was used to design an operational transconductance amplifier current-mirror as a core of an AC-coupled Amplifier. So, AC-coupled amplifier applications were discussed, as well as an overview of the analog integrated circuit design flow and the open-source EDA tools used in each step. Simulations and results are presented and compared with other works in the state of the art. The performance of open-source tools and open-source process design kit are properly assessed. © 2022 ieee.

关键词： Operational amplifiers

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