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Low-Power Quadrature VCO design for Medical Implant Communication Service

Low-Power Quadrature VCO Design for Medical Implant Communic...

引用

14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kim, Jeong Ki Jeong, Jihoon Ha, Dong Sam Lee, Hyung-soo Virginia Tech Bradley Dept Elect & Comp Eng Blacksburg VA 24061 USA ETRI Green Comp Res Div Daejeon 307700 South Korea

ISBN: (纸本)9781424497560

This paper presents two different implementations of a low-power quadrature frequency source generator for medical implant communication service (MICS) applications. The first circuit uses a current-reuse VCO running at double the target frequency followed by a divide-by-two frequency divider. The circuit dissipates only 230 mu W and achieves low phase noise of - 127 dBc/Hz@1MHz. The second one adopts a parallel-coupling scheme to combine two current-reuse VCOs (P-QVCO). The circuit exhibits a moderate power consumption of 960 mu W and achieves very low phase noise of -138 dBc/Hz@1MHz.

关键词： MICS QVCO Current-reuse VCO P-QVCO

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An extension of transient fault emulation techniques to circuits with embedded memories

An extension of transient fault emulation techniques to circ...

引用

9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Garcia-Valderas, Mario Portela-Garcia, Marta Lopez-Ongil, Celia Entrena, Luis Univ Carlos III Madrid Microelect Grp Elect Technol Dept Madrid Spain

ISBN: (纸本)1424401844

Fault injection is commonly used for evaluation of fault tolerance of safety-critical systems. Among the possible fault injection techniques, FPGA-based emulation is very attractive because of its superior performance. In particular, Autonomous Emulation technique can provide emulation speeds in the order of millions of faults per second. In this paper FPGA-based emulation is extended to circuits with embedded memories. To this purpose, an instrumented memory model is proposed that can be progressively enhanced to increase accuracy at the cost of a larger overhead. Also, an efficient fault injection mechanism is described. This model can be integrated in a seamless manner in an Autonomous Emulation system, as it is demonstrated using the LEON2 processor benchmark.

关键词： Digital circuits

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Measurement Point Selection for In-Operation Wear-Out Monitoring

Measurement Point Selection for In-Operation Wear-Out Monito...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ingelsson, Urban Chang, Shih-Yen Larsson, Erik Linkoping Univ Dept Comp & Informat Sci S-58183 Linkoping Sweden

ISBN: (纸本)9781424497560

In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wear-out monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

关键词： Circuit faults Delay Electromigration IC designs Integrated circuit interconnections Monitoring Wireless sensor networks circuitry on-chip electromigration electromigration wear-out in-operation wear-out monitoring integrated circuit design measurement point selection monitoring

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FPGA design of the Computation Unit for the Semi-Global Stereo Matching Algorithm 17

FPGA design of the Computation Unit for the Semi-Global Ster...

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Roszkowski, Mikolaj Pastuszak, Grzegorz Warsaw Univ Technol Inst Radioelect PL-00661 Warsaw Poland

ISBN: (纸本)9781479945580

In recent years, it is possible to observe an increased interest in methods of stereo-vision as they allow simple 3D representations of the scene acquired with two optical cameras. However, not all methods described in literature are suitable for a real-time implementation in hardware. One method generally considered to produce good results and viable for such an implementation is semi-global stereo matching. Nevertheless, there are not many in-depth descriptions of hardware architectures of modules implementing this method in the literature. In this article we try to fill in this gap by presenting a detailed FPGA-oriented architecture of the basic computation unit supporting the semi-global matching algorithm. The unit is responsible for carrying out all calculation necessary to select the best disparity for each pixel. We also present a novel solution to the problem of storing paths' costs for each pixel and discuss the trade-offs between the size of the unit in an FPGA chip and precision of the computed disparity map.

关键词： pixel Field programmable gate arrays Stereoviews arithmetic Literature Computer hardware ARCHITECTURE

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Integrated sensors for early breast cancer diagnostics 21

Integrated sensors for early breast cancer diagnostics

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21st ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Farag, Omar Mohamed, Mariam Ghany, Mohamed A. Abd El Hofmann, Klaus German Univ Cairo Elect Engn Dept Cairo Egypt Tech Univ Darmstadt Integrated Elect Syst Lab Darmstadt Germany

ISBN: (纸本)9781538657546

A wearable, low cost and power efficient early breast cancer detection device is proposed. Bioimpedance spectroscopy (BIS) and near infrared spectroscopy (NIRS) are used. The NIRS and BIS sensors differentiate between normal and cancerous breasts according to their optical and electrical properties respectively. The bioimpedance spectroscopy sensor measurements are carried out by a multi-step frequency sweep. The near infrared spectroscopy sensor uses multi-wavelengths LEDs with optical filters. The results obtained by NIRS and BIS sensors are combined together in the control unit. A custom designed mobile application is connected with the device through Bluetooth. The proposed device was tested in vitro using tissue like mimicking phantoms stimulating the electrical and the optical properties of the normal and cancerous breast tissues. The proposed system shows accuracy of 99.3% and low power consumption of 80mW.

关键词： Breast cancer Bioimpedance spectroscopy near infrared spectroscopy lambert beer theory phantom

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Parity Waterfall Method 19

Parity Waterfall Method

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Borecky, Jaroslav Kohlik, Martin Kubatova, Hana Czech Tech Univ Dept Digital Design Fac Informat Technol Tech 9 Prague Czech Republic

ISBN: (纸本)9781509024674

This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. The utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. The method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. The experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). These results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.

关键词： Field programmable gate arrays (FPGA)

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Pca data preprocessing for neural network-based detection of parametric defects in analog ic

Pca data preprocessing for neural network-based detection of...

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Malosek, P. Stopjakova, V. Slovak Tech Univ Dept Microelect Ilkovicova 3 Bratislava 81219 Slovakia

ISBN: (纸本)1424401844

A new methodology for algorithmic selection of a proper training vector set for neural network learning in 2D PCA space is presented. In feed-forward neural networks with un-supervised learning, the training set selection plays a crucial role. In this paper, we propose a new approach to this selection using convex-hull graphics algorithms. Feed-forward neural network has been used for detecting parametric defects in a band pass filter circuit. As it is shown, well trained neural network is not only able to detect the faulty devices by classifying the analysed circuit's parameter into a proper category but also identifies direction of an undesired deviation of the parameter.

关键词： Integrated circuits

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New current monitor using auto zero voltage comparator for I_DD testing of mixed-signal circuits

New current monitor using auto zero voltage comparator for I...

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9th ieee Workshop on design and diagnostics of electronic circuits and systems

作者： Nagy, Vladislav Stopjakova, Viera Slovak Univ Technol Bratislava Dept Microelect Ilkovicova 3 Bratislava 81219 Slovakia

ISBN: (纸本)1424401844

An approach to the dynamic supply current sensing based on the measurement of voltage drop across a parasitic resistance of the supply voltage metal routing is presented. Auto-zero technique for voltage comparator offset cancellation, which provides very accurate and sensitive low voltage drop measurement is proposed. Therefore, one may use the proposed sensor as a current monitor for dynamic current testing of mixed-signal circuits without any additional element necessarily connected in series with the power supply line. The proposed current monitor was designed in a 0.35 mu m CMOS technology.

关键词： Comparator circuits

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A Memetic Algorithm for Computing 3D Capacitance in Multiconductor VLSI circuits

A Memetic Algorithm for Computing 3D Capacitance in Multicon...

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14th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Bontzios, Yiorgos I. Dimopoulos, Michael G. Hatzopoulos, Alkis A. Aristotle Univ Thessaloniki Dept Elect & Comp Eng GR-54006 Thessaloniki Greece Alexander Technol Educ Inst Thessaloniki Dept Elect Thessaloniki Greece

ISBN: (纸本)9781424497560

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

关键词： Capacitance Capacitance Modeling Point Charges Method of Images VLSI circuits Memetic Algorithm

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On the Mitigation of SET broadening effects in Integrated circuits

On the Mitigation of SET broadening effects in Integrated Ci...

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13th ieee symposium on design and diagnostics of electronic circuits and systems

作者： Sterpone, Luca Battezzati, Niccolo Politecn Torino Dip Automat & Informat Turin Italy

ISBN: (纸本)9781424466139

Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event Transient (SET) pulses that may be generated and propagated through the combinational logic, leading to misbehaviors. SETs are mainly generated by high-energy particles that strikes the circtuit near a junction, resulting in a significant charge injection/depletion process, that may produce spurious pulses. These can propagate and change their shape traversing the combinational logic paths, sometimes being broadened and amplified sometimes being filtered. In this paper, we present a place and route algorithm for integrated circuit design, which is able to mitigate and filter the erroneous effects of SETs. The proposed solution has been experimentally evaluated by means of electrical pulse injection within logic resources of several benchmark Integrated circuits (ICs) implemented in a Flash-based FPGA and by accurate timing analyses. Preliminary results confirm the mitigation of SET broadening effects by acting on physical place and route constraints. On the selected benchmark circuit the algorithm decreases the SET sensitiveness more than 70% with respect to not hardened circuits. Besides, the solution does not introduce any area overhead or delay penalties.

关键词： Integrated circuit design

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