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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Live Demonstration: A High-frame-rate and Energy-efficient SIFT Feature Extraction Accelerator Based SoC design for AMR Applications

Live Demonstration: A High-frame-rate and Energy-efficient S...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Zhenhui Duan Bingqiang Liu Zehua Yin Jipeng Wang Zixuan Shen Xupeng Zhang Zaisheng He Chao Wang School of Integrated Circuit Huazhong University of Science and Technology Wuhan China School of Optical and Electronic Information Huazhong University of Science and Technology Wuhan China Amicro Semiconductor Company Ltd Zhuhai China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

This demonstration presents a high-frame-rate and energy-efficient Scale-Invariant Feature Transform (SIFT) feature extraction accelerator based System on Chip (SoC) design. The platform implementing SIFT-based object recognition consists of an OV5640 camera, a SIFT hardware accelerator based on the ZYNQ-7000 SoC, and a personal computer (PC). The feature points and recognition results are displayed on the monitor in real-time at 60 frames per second (fps) with QVGA resolution for Autonomous Mobile Robot (AMR) applications.

关键词： Robot vision systems Transforms Microcomputers Feature extraction Energy efficiency Real-time systems System-on-chip

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design of Magnetic Field Acquisition Probe and Front-End Signal Processing Circuit

Design of Magnetic Field Acquisition Probe and Front-End Sig...

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ieee International symposium on circuits and systems (ISCAS)

作者： Guoqiang Li Yongfang Liu Yuanjin Zheng School of Electrical and Electronic Engineering Nanyang Technological University Singapore Chinese Academy of Sciences Shanghai Advanced Research Institute Shanghai China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

This paper focuses on the acquisition and front-end processing of magnetic field information in pulsed magnetic field measurements. Based on the Faraday electromagnetic induction principle, a magnetic field measurement probe was designed, and a front-end processing circuit for pulse magnetic field induction electromotive force was developed for this probe. The sensing probe has a MHz bandwidth response capability, making it well-suited for covering pulse magnetic field applications. The front-end processing circuit is based on analog operational amplifiers and integrates amplification, filtering, and integration circuits. Finally, PSpice simulation software was used to simulate the design. The simulation results, along with experimental results, demonstrate that the magnetic field probe and front-end processing circuit designed in this paper have advantages such as high bandwidth and fast response.

关键词： Magnetic field measurement Magnetic separation Electromagnetic induction Electric variables measurement Bandwidth Magnetic analysis Probes

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RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator

RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microar...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Josiah Mendes Rajesh C. Panicker Department of Electrical and Computer Engineering National University of Singapore Singapore Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Riscalar is a highly parameterisable, extensible, and modular computer architecture simulation tool designed for the RISC-V ISA. The ability of Riscalar to explore a large design space with configurable pipeline widths, execution orders, functional units, cache sizes, and branch predictors differentiates it from other RISC-V educational simulators. It is capable of simulating user-designed programs through standard cross-compilation tools, and can be used to explore the relationship between processor microarchitecture, compiler optimizations, and program performance. This paper details the design and implementation of Riscalar using Rust, highlighting the abstractions made to implement a cycle-approximate simulator.

关键词： Microarchitecture Program processors Source coding Pipelines Education Computer architecture Documentation

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Standard Cell Tuning Enables Data-Independent Static Power Consumption 23

Standard Cell Tuning Enables Data-Independent Static Power C...

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23rd ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Belohoubek, Jan Fiser, Petr Schmidt, Jan Czech Tech Univ Fac Informat Technol Prague Czech Republic

ISBN: (纸本)9781728199382

Physical attacks, namely invasive, observation and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light-modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance traditional static CMOS bulk structures. To enable data dependency hiding, we propose low-level techniques based on complementary-value induced balancing currents, constant current source behavioral approximation, and light-sensing capability of traditional CMOS structures. The proposed techniques may be used to build a dual-rail circuit balanced from both perspectives: static and dynamic power. The publicly available TSMC180nm node standard cell simulation is used for evaluation.

关键词： CMOS integrated circuits

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Minimax design of M-D Interpolated FIR Filters using Convex-Concave Procedure

Minimax Design of M-D Interpolated FIR Filters using Convex-...

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ieee International symposium on circuits and systems (ISCAS)

作者： Pathmapirian Nanthakumar Chamira U. S. Edussooriya Chamith Wijenayake Arjuna Madanayake School of Electrical Engineering and Computer Science University of Queensland Brisbane Australia Department of Electronic and Telecommunication Engineering University of Moratuwa Moratuwa Sri Lanka Department of Electrical and Computer Engineering Florida International University Miami USA

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

We propose a minimax design method for multi-dimensional (M-D) interpolated finite-support impulse response (IFIR) filters. As a result of the cascade structure of an MD IFIR filter, the optimization problem of the minimax design is nonconvex. In order to solve this nonconvex optimization problem, we employ a convex-concave procedure, where each iteration solves a convex constrained optimization problem. We present experimental results to confirm the effectiveness and the superior performance of the proposed method compared to previously proposed minimax designs of M-D IFIR filters. Furthermore, we present an implementation of M-D IFIR filter on the Xilinx Kintex UltraScale KCU105 field-programmable gate array, where a quantization error of −60.59 dB is achieved with the coefficient word length of 24 bits.

关键词： Filters Quantization (signal) Finite impulse response filters circuits and systems design methodology Computational complexity Optimization

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Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization 34

Accuracy and Size Trade-off of a Cartesian Genetic Programmi...

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34th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design (SBCCI)

作者： Berndt, Augusto De Abreu, Brunno A. Campos, Isac S. Lima, Bryan Grellert, Mateus Carvalho, Jonata T. Meinhardt, Cristina Univ Fed Santa Catarina UFSC PPGCC Dept Informat & Estat Florianopolis SC Brazil Univ Fed Rio Grande do Sul UFRGS Inst Informat PGMicro Porto Alegre RS Brazil

ISBN: (纸本)9781665421706

Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Traditional approaches for logic synthesis have been in the spotlight so far. However, due to advances in machine learning and their high performance in solving specific problems, such algorithms appear as an attractive option to improve electronic design tools. In our work, we explore Cartesian Genetic Programming for logic optimization of exact or approximate combinational circuits. The proposed CGP flow receives input from the circuit description in the format of AND-Inverter Graphs and its expected behavior as a truth-table. The CGP may improve solutions found by other techniques used for bootstrapping the evolutionary process or initialize the search from random (unbiased) individuals seeking optimal circuits. We propose two different evaluation methods for the CGP: to minimize the number of AIG nodes or optimize the circuit accuracy. We obtain at least 22.6% superior results when considering the ratio between accuracy and size for the benchmarks used, compared with the teams from the IWLS 2020 contest that obtained the best accuracy and size results. It is noteworthy that any logic synthesis approach based on AIGs can easily incorporate the proposed flow. The results obtained show that their usage may achieve improved logic circuits.

关键词： Cartesian Genetic Programming electronic design Automation Logic Optimization Machine Learning

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EDA for Domain Specific Computing An Introduction for the Panel 23

EDA for Domain Specific Computing An Introduction for the Pa...

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International symposium on Physical design (ISPD)

作者： Jiang, Iris Hui-Ru Chinnery, David Natl Taiwan Univ Taipei Taiwan Siemens Digital Ind Software Fremont CA USA

ISBN: (纸本)9781450399784

This panel explores domain-specific computing from hardware, software, and electronic design automation (EDA) perspectives. Hennessey and Patterson signaled a new "golden age of computer architecture" in 2018 [1]. Process technology advances and general-purpose processor improvements provided much faster and more efficient computation, but scaling with Moore's law has slowed significantly. Domain-specific customization can improve power-performance efficiency by orders-of-magnitude for important application domains, such as graphics, deep neural networks (DNN) for machine learning [2], simulation, bioinformatics [3], image processing, and many other tasks. The common features of domain-specific architectures are: 1) dedicated memories to minimize data movement across chip;2) more arithmetic units or bigger memories;3) use of parallelism matching the domain;4) smaller data types appropriate for the target applications;and 5) domain-specific software languages. Expediting software development with optimized compilation for efficient fast computation on heterogeneous architectures is a difficult task, and must be considered with the hardware design. For example, GPU programming has used CUDA and OpenCL. The hardware comprises application-specific integrated circuits (ASICs) [4] and systems-of-chips (SoCs). General-purpose processor cores are often combined with graphics processing units (GPUs) for stream processing, digital signal processors, field programmable gate arrays (FPGAs) for configurability [5], artificial intelligence ( AI) acceleration hardware, and so forth. Domain-specific computers have been deployed recently. For example: the Google Tensor Processing Unit (DNN ASIC) [6];Microsoft Catapult (FPGA-based cloud domain-service solution) [7];Intel Crest (DNN ASIC) [8];Google Pixel Visual Core (image processing and computer vision for cell phones and tablets) [9];and the RISC-V architecture and open instruction set for heterogeneous computing [10].

关键词： Domain specific computing electronic design automation

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3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications

3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating...

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ieee International symposium on circuits and systems (ISCAS)

作者： Zhangyi Pei Vishnu P. Nambiar Yi Sheng Chong Wang Ling Goh Anh Tuan Do Institute of Microelectronics A*STAR (Agency for Science Technology and Research) Singapore School of Electrical and Electronic Engineering Nanyang Technological University Singapore

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

An efficient and extremely low-energy AES-256 accelerator was implemented in a 40nm CMOS process for space and energy-limited IoT applications, supporting encryption, decryption, ECB and CBC modes. By reusing functional block hardware and utilizing scan flip-flops, the proposed AES design occupies merely 3005 µm of silicon area. Additionally, clock gating circuits were extensively used at circuit level to halt essential flip-flops during the ShiftRows and its reversed operation for aggressive power saving. The post-layout simulation showed that our proposed design achieved the lowest power consumption of 1.83 µW at 0.3 V, 17 MHz, with energy efficiency as high as 3881 Gbps/W.

关键词： Power demand circuits Logic gates Silicon Energy efficiency Internet of Things Low-power electronics

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design of SIW Filtering Power Dividers Based on Fractal Metamaterial Slotted Resonators

Design of SIW Filtering Power Dividers Based on Fractal Meta...

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2024 Photonics and Electromagnetics Research symposium, PIERS 2024

作者： He, Zhilin Cao, Xin Cai, Qiangming Zhou, Longjian Li, Haoran Zhu, Yuyu Southwest University of Science and Technology School of Information Engineering Mianyang621010 China South China University of Technology School of Electronic and Information Engineering Guangzhou510640 China

ISBN: (纸本)9798350375909

With the development of new generation wireless communication technology, microwave devices are developing towards miniaturization and integration. Power dividers are important components of the transmitter, their size and performance can influence the quality of communication systems greatly. Therefore, in order to decrease the size of the power dividers and to reduce component size, this paper proposes several substrate integrated waveguide (SIW) power dividers based on fractal metamaterial slotted resonators. First, planar geometrical fractals such as the Minkowski fractals, Hilbert fractals and von Koch fractals have been applied in the SIW structure as slots. Due to the slow wave effects, the size of the proposed SIW can be reduced compared with conventional SIWs. Then by loading slotted resonators, the filtering characteristics can also be achieved. To verify the performance of the proposed structure, three SIW power division filters have been designed based on these proposed fractal metamaterial slotted resonators. The input and output of the power division filters are connected with tapered microstrip lines with the port characteristic impedance of 50 ohms. As the full-wave simulated results show that the proposed power division filters can achieve a filter band from 9 GHz to 11.9 GHz with the in-band S11 better than -10 dB. Based on the electric field distribution, it can also be observed that the size has been reduced. Further improvements have been achieved. Our proposed structures are easy to manufacture and can be applied in the modern wireless communication circuits and systems. © 2024 ieee.

关键词： Substrate integrated waveguides

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Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing 23

Mont-Blanc 2020: Simulation Efforts Towards Exascale High Pe...

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23rd ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Nocua, Alejandro Derradji, Said Vaumourin, Gregory Lagadec, Pierre-Axel Menyhart, Zoltan BULL Atos Technol Ave Jean Jaures F-78340 Les Clayes Sous Bois France

ISBN: (纸本)9781728199382

The Mont-Blanc project follows a co-design approach to ensure the final hardware design meets real-world High-Performance Computing (HPC) application requirements. Simulation is widely used in system design for evaluating different design options, as well as to characterize how an application will run in that configuration. The main idea is to test the applications and evaluate future performance prior to silicon availability. One of the most widely used simulation tools in research and in the Mont-Blanc series project is the gem5 simulator. gem5 is an open source, modular platform for computer-system architecture that is flexible and highly configurable. It can model a whole system architecture as it includes different models for the cores and the memory hierarchy. The objective of this tutorial, is to present in a our simulation framework, and how it has help on the design of highly complex systems.

关键词： ARM HPC Co-design gem5 Mont-Blanc 2020

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