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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Lazy Man’s Resynthesis For Glitching-Aware Power Minimization

Lazy Man’s Resynthesis For Glitching-Aware Power Minimizati...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Andrea Costamagna Xiaoqing Xu Giovanni De Micheli Dino Ruic Google DeepMind Mountain View USA Integrated Systems Laboratory EPFL Lausanne Switzerland

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

This paper presents a novel resynthesis engine for minimizing the dynamic power of digital circuits. Traditional logic synthesis methods primarily focus on zero-delay toggles—logic state changes occurring between the start and end of a clock cycle. In contrast, our engine targets both zero-delay toggles and glitches, unintended transitions within a clock cycle caused by path imbalances. Glitches significantly contribute to power consumption in arithmetic circuits, making their minimization a critical challenge in electronic design. The proposed method uses a database of Pareto-optimal netlists to replace sub-networks in the target circuit with power-efficient alternatives. These replacements are guided by a simulation-driven cost function that evaluates workload-independent switching activity and penalizes gates with high fan-out. We call our approach Lazy Man’s Resynthesis because it builds on an algorithm named Lazy Man’s Synthesis, extending it from technology-independent delay optimization to post-mapping power optimization. Applied to the ISCAS and EPFL benchmarks, our method reduces glitching activity by 4.72% and dynamic power by 9.44%, achieving a 7.61% improvement over the state-of-the-art.

关键词： Power demand Heuristic algorithms Switches Logic gates Minimization Logic Engines electronic circuits Digital circuits Clocks

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Mitigating DoS Attacks on CAN: A Priority-Raise Approach and Its Timing Analysis

Mitigating DoS Attacks on CAN: A Priority-Raise Approach and...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mingqing Zhang Alejandro Masrur Department of Computer Science TU Chemnitz Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

With an increasing level of interconnection, it has become easier for attackers to target in-vehicle buses in industrial and road vehicles alike. One of the most common attacks is Denial-of-Service (DoS), where the bus is flooded with messages disrupting critical functions and, thereby, jeopardizing the safety of operators and/or passengers. In this paper, we are concerned with DoS attacks on Controller Area Network (CAN) – one of the most popular buses – and propose a priority-raise approach (PRA) to mitigate their impact. Basically, we limit the priority of messages arriving through a gateway from outside the vehicle. If a DoS attack is started, this only affects the messages with lower priority than that used by the attacker. Affected messages can then switch to a higher priority reserved for them, i.e., they can raise their priority, to escape the attack. We investigate a centralized as well as a decentralized priority switching and analyze timing for a varying DoS severity.

关键词： Road vehicles Switches Logic gates Denial-of-service attack Safety Delays Controller area networks electronic circuits Vehicles Cruise control

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An Innovative Data Mining Technique for Automatic Anomaly Detection in Physical Unclonable Functions

An Innovative Data Mining Technique for Automatic Anomaly De...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mohammad Reza Heidari Iman Sergio Vinagrero Gutierrez Elena-Ioana Vatajelu Giorgio Di Natale CNRS Grenoble INP* TIMA Univ. Grenoble Alpes Grenoble France Institut des Nanotechnologies de Lyon (INL)

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Physical Unclonable Functions (PUFs) offer a promising alternative to conventional cryptographic techniques to secure sensitive information in modern circuits. PUFs leverage inherent process variability to dynamically generate unique secrets, eliminating the need for data storage. However, a significant challenge in PUF-based security is differentiating between valid PUFs and those that may have been tampered with or are invalid (i.e., not belonging to the original design). This paper presents an innovative data mining-based technique for detecting anomalies and identifying tampered or invalid PUFs. The proposed method extracts a set of rules that describe the expected behavior of the PUF, where deviations from these rules indicate potential security issues and vulnerabilities. Experimental results demonstrate that the method effectively detects invalid or tampered PUFs, highlighting its potential to strengthen PUF-based security systems.

关键词： Correlation Accuracy Memory Physical unclonable function Data models Association rule learning Cryptography Integrated circuit modeling Anomaly detection electronic circuits

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CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution

CrosSym: Cross-Level Verification of SystemC Peripherals usi...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Karl Aaron Rudkowski Sallar Ahmadi-Pour Rolf Drechsler Institute of Computer Science University of Bremen Bremen Germany Cyber-Physical Systems DFKI GmbH Bremen Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Modern hardware design is challenged by the ever-increasing complexity of designs. An important step is hardware verification, where Virtual Prototypes (VPs) can be used for a cross-level verification throughout the refinements. Peripherals are relevant targets, because they characteristically implement a wide range of integral tasks. Symbolic execution is a popular verification method, but has been applied to SystemC peripherals only once, and never for a cross-level verification. We propose CrosSym, the first method to verify peripherals at both Register Transfer Level (RTL) and Transaction Level Modelling (TLM) abstraction with symbolic execution, explicitly supporting cross-level. Our extensive evaluation explores (1) the performance costs of two abstraction levels, (2) our approach’s suitability for a full verification, using three peripherals, (3) it’s bug finding capabilities by killing over 1500 mutants in under 15 min. In the latter, most scenarios found 97+% of the observable mutations.

关键词： Costs Computer bugs Prototypes Register transfer level Hardware Complexity theory Object recognition Kernel electronic circuits

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Millimeter-wave GaAs Rectifier with Differential Signal 4:1 Power Combiner for Simultaneous Wireless Information and Power Transmission 16

Millimeter-wave GaAs Rectifier with Differential Signal 4:1 ...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Kikuchi, Masayuki Ide, Michihiro Mayeda, Jill Kato, Sena Yuasa, Keito Okada, Kenichi Shirane, Atsushi Institute of Science Tokyo Dept. Electrical and Electronic Engineering 2-12-1-S3-28Ookayama Meguro-ku Japan

ISBN: (纸本)9798331522124

This paper presents a rectifier with a power combiner for a millimeter-wave wireless power transmission system. The proposed circuit uses a diode fabricated in a 0.1 um GaAs process for rectification and mixing, and a metal layer create a transformer to synthesize the power. The rectifier and power synthesizer are integrated into a single chip. The chip has four input ports for 24 GHz WPT differential signals and 25 GHz RF differential signals, and one output port for DC and 1 GHz IF single-ended signals. The DC output can operate with a 100Ω load. For power generation, the most efficient DC conversion is achieved at 25.4GHz signal, where with a total input power of 26.2 dBm, DC conversion efficiency is 10.8%. The maximum DC power obtained is 51.8mW. As a mixer, it achieves a down-conversion gain of -15.6 dB. © 2025 ieee.

关键词： Antenna phased arrays

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S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors

S4V: A Benchmark Suite of Transient Execution Attacks for RI...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Elia Lazzeri Matteo Colella Gianluca Furano Luca Cassano Politecnico di Milano Milano Italy European Space Agency Noordwijk The Netherlands

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Transient Execution Attacks (TEAs) exploit architectural optimizations in modern processors, such as out-of-order and speculative execution, to illicitly access sensitive data belonging to other processes or the operating system. While the RISC-V ISA has gained significant traction, its susceptibility to TEAs remains relatively unexplored. A major obstacle to in-depth security evaluation of RISC-V processors is the lack of readily accessible and comprehensive TEA implementations for these architectures. This paper introduces Security for RISC-V (S4V), a security benchmark suite comprising implementations of several recent TEAs specifically tailored for RISC-V processors. Beyond providing a template for each TEA implementation, we developed an instance of S4V for the Berkeley Out-of-Order Machine (BOOM) processor to demonstrate the feasibility of executing these attacks on a widely adopted and renowned RISCV core. S4V aims to facilitate security research in evaluating countermeasures and enabling a more thorough understanding of TEA vulnerabilities within the RISC-V ecosystem.

关键词： Out of order Program processors Operating systems Microprocessors Hardware security Benchmark testing Transient analysis electronic countermeasures Optimization electronic circuits

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Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators

Bridging Quantization and Deployment: A Fixed-Point Workflow...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Obed M. Mogaka Håkan Forsberg Masoud Daneshtalab DeepHERO lab Mälardalen University Sweden Tallinn University of Technology Estonia

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Deploying deep learning models on resource-constrained hardware like Field-Programmable Gate Arrays (FPGAs) remains challenging despite advancements in quantization techniques, which often fail to map optimally to target hardware. This study proposes an end-to-end workflow for fixed-point quantization targeting FPGA accelerators, integrating hardware emulation within quantization-aware training to bridge software-hardware co-design. This ensures quantized models are optimized for real-world deployment. Evaluations on CIFAR-10 and ImageNet datasets using ResNet and VGG models show competitive performance, with up to 2% improvement in accuracy over state-of-the-art methods. This work provides insights to resolve the discrepancies that often occur between software-based quantization and hardware deployment. Our methodology effectively bridges quantization and deployment, providing a practical solution for edge device applications.

关键词： Performance evaluation Deep learning Training Quantization (signal) Image resolution Image edge detection Emulation Bridge circuits Hardware Field programmable gate arrays

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A Low-Power Level-2 Discrete Haar Wavelet Transform with Approximate Adders for ECG Signal 16

A Low-Power Level-2 Discrete Haar Wavelet Transform with App...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Seidel, Henrique Da Rosa, Morgana Lopes, Rodrigo Da Costa, Eduardo Soares, Rafael Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil

ISBN: (纸本)9798331522124

We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-established approximate adders (AxPPA, COPY, ETA-I, LOA, and Trunc) and bit truncation (T), to reduce energy consumption while maintaining accuracy above 99% for reliable R-peak detection. By focusing on the second-level detail coefficient (D2) for peak detection and pruning the approximation coefficient, the PDHWT-2 design achieves significant reductions in computational complexity. The architecture, evaluated with ECG signals from the MIT-BIH database, maintained accuracy above 99% even with aggressive bit truncation and approximation, ensuring reliable medical-grade analysis. Integration of approximate adders (AxAs) and truncation enabled significant power and area savings. Specifically, the use of the AxPPA demonstrated power savings of up to 40% with area reductions of around 45%, making the PDHWT-2 a highly efficient solution for low-power ECG monitoring systems. © 2025 ieee.

关键词： Image reconstruction

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Exploring Approximate Adders for Accuracy- and Energy-Quality VLSI Watermarking systems design 16

Exploring Approximate Adders for Accuracy- and Energy-Qualit...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Da Rosa, Morgana Da Costa, Eduardo Soares, Rafael Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil

ISBN: (纸本)9798331522124

Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves exploring different approximation adder (AxA) configurations as a viable form of reducing power consumption in many applications. This work explores the use of AxAs in a hybrid watermarking technique that combines discrete Haar-Wavelet (DHWT) and discrete cosine transforms (DCT). The proposed hybrid method, HyDHWCT, integrates these transforms to improve robustness and imperceptibility in watermarking systems while optimizing for energy efficiency. We evaluate the performance of various AxAs, including Copy, ETA, LOA, Truncation (Trunc), VLSPPAs, and the AxPPA, regarding energy consumption, circuit area, and error resilience. Our results demonstrate that the AxPPA-based HyDHWCT offers superior accuracy and energy-quality trade-offs over other state-of-the-art AxAs. Specifically, the AxPPA on HyDHWCT with K = 1 achieves up to 72.85% energy savings and 88.32% area savings compared to the exact HyDHWCT while maintaining high accuracy, with a normalized cross-correlation (NC) of 0.9949 and a structural similarity (SSIM) of 0.9920 for the extracted watermark. These results make the AxPPA-based HyDHWCT a highly effective solution for robust and energy-efficient watermarking systems. © 2025 ieee.

关键词： Energy efficiency

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Implementation of Dynamic SISD-SIMD Integer Dividers

Implementation of Dynamic SISD-SIMD Integer Dividers

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Gianluca Radi Ares Tahiraga Robert Kunzelmann Ties Jan Henderikus Kluter Wolfgang Ecker Processor Architecture Laboratory EPFL Lausanne Switzerland Infineon Technologies AG Neubiberg Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Digital division is a pivotal operation in a number of domains, such as scientific computation, cryptography, digital signal processing, and machine learning, and has been broadly researched in the past decades. However, the increasing demand for efficient digital systems has emphasized the design of digital dividers with more stringent area and power costs without excessively compromising their performance. One option to achieve this is to implement Single Instruction Multiple Data (SIMD) dividers capable of exploiting the abundance of data-level parallelism, which is naturally present in common tasks such as stream processing, matrix normalization, and vector scaling. In this paper, we propose the designs of four configurable integer dividers capable of sustaining both Single Instruction Single Data (SISD) and SIMD computations, targeting different levels of performance and efficiency. Compared to one of the state-of-the-art integer dividers, our most efficient SIMD divider shows a 54% smaller area and 30% lower power consumption. Furthermore, we propose a novel technique which can reduce n-bit divisions to smaller (n−m)-bit ones, yielding a peek speedup of 15% when implemented in one of our proposed dividers.

关键词： Costs Power demand Single instruction multiple data Digital systems Machine learning Digital signal processing Frequency conversion Vectors Cryptography electronic circuits

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