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electronic design considerations and system development for structural health monitoring with ultrasonic guided waves

Electronic design considerations and system development for ...

引用

2024 ieee Ultrasonics, Ferroelectrics, and Frequency Control Joint symposium

作者： Capineri, Lorenzo Univ Firenze Dipartimento Ingn Informaz Florence Italy

ISBN: (纸本)9798350371918;9798350371901

The design of electronic systems for structural health monitoring (SHM) with ultrasonic guided waves (UGW) requires a dedicated electronic front-end considering the peculiarities of this application. The UGW piezoelectric transducers characteristics are first decided depending on the operating environment, the structures material and their dimensions, the definition of connections and transducers diagnostics. Another specific feature of the electronic design is for the systems operating both in passive mode for impact detection and active mode for damage detection and positioning. These two operating modes correspond to different analog electronic chains because the received signals have different amplitude levels and frequency spectrum. The paper will review the main building blocks of the electronic system with a focus on analog front-end electronic circuits.

关键词： Ultrasonic Guided Waves Structural Health Monitoring electronic system design analog front-end piezoelectric sensors network

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Prediction of Inference Energy on CNN Accelerators Supporting Approximate circuits 26

Prediction of Inference Energy on CNN Accelerators Supportin...

引用

26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Pinos, Michal Mrazek, Vojtech Sekanina, Lukas Brno Univ Technol Brno Czech Republic

ISBN: (纸本)9798350332773

design methodologies developed for optimizing hardware implementations of convolutional neural networks (CNN) or searching for new hardware-aware neural architectures rely on the fast and reliable estimation of key hardware parameters, such as the energy needed for one inference. Utilizing approximate circuits in hardware accelerators of CNNs faces the designers with new problems during their simulation commonly used tools (TimeLoop, Accelergy, Maestro) do not support approximate arithmetic operations. This work addresses the fast and efficient prediction of consumed energy in hardware accelerators of CNNs that utilize approximate circuits such as approximate multipliers. First, we extend the state-of-the-art software frameworks TimeLoop and Accelergy to predict the inference energy when exact multipliers are replaced with various approximate implementations. The energies obtained using the modified tools are then considered the ground truth (reference) values. Then, we propose and evaluate, using two accelerators (Eyeriss and Simba) and two types of networks (CNNs generated by EvoApproxNAS and standard ResNet CNNs), two predictors of inference energy. We conclude that a simple predictor based on summing the energies needed for all multiplications highly correlates with the reference values if the CNN's architecture is fixed. For complex CNNs with variable architectures typically generated by neural architecture search algorithms, a more sophisticated predictor based on a machine learning model has to be employed. The proposed predictors are 420-533x faster than reference solutions.

关键词： Timing circuits

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A Reliability-aware Environment for design Exploration for GPU Devices 26

A Reliability-aware Environment for Design Exploration for G...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Sierra, Robert Limas Guerrero-Balaguera, Juan-David Condia, Josie E. Rodriguez Reorda, Matteo Sonza Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy

ISBN: (纸本)9798350332773

Nowadays, GPU platforms have gained wide importance in applications that require high processing power. Unfortunately, the advanced semiconductor technologies used for their manufacturing are prone to different types of faults. Hence, solutions are required to support the exploration of the resilience to faults of different architectures. Based on this motivation, this work presents an environment dedicated to the analysis of the impact of permanent faults on GPU platforms. This environment is based on GPGPU-Sim, with the objective of exploiting the configuration features of this tool and, thus, analyzing the effects of faults when changing the target architecture. To validate the environment and show its usability, a fault campaign has been carried out where three different GPU architectures (Kepler, Volta, and Turing) were used. In addition, each GPU has been modified with an arbitrary number of parallel processing cores (or SMs). Three representative applications (Vector Add, Scalar Product, and Matrix Multiply) were executed on each GPU, and the behavior of each architecture in the presence of permanent faults in the functional (i.e., integer unit and floating-point) units was analyzed. This fault campaign shows the usability of the environment and demonstrates its potential use to support decisions on the best architectural parameters for a given application.

关键词： Architectural models design exploration Graphics Processing Units (GPUs) Permanent faults Reliability

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Proceedings - 2021 24th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2021

Proceedings - 2021 24th International Symposium on Design an...

引用

24th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2021

ISBN: (纸本)9781665435956

The proceedings contain 31 papers. The topics discussed include: development of on-chip calibration for hybrid pixel detectors;enhanced reliability of fully differential difference amplifier through on-chip digital calibration;design and implementation strategy of adaptive processor-based systems for error resilient and power-efficient operation;analysis of state corruption caused by permanent faults in WCHB-based quasi delay-insensitive pipelines;on the functional test of special function units in GPUs;AdequateDL: approximating deep learning accelerators;approximate multipliers for optimal utilization of FPGA resources;accelerated analysis of simulation dumps through parallelization on multicore architectures;Q-learning-based routing algorithm for 3D network-on-chips;and EKV MOS transistor model for ultralow-voltage bulk-driven IC design.

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design Automation for Charge Recovery Logic

Design Automation for Charge Recovery Logic

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ieee International symposium on circuits and systems (ISCAS)

作者： Gonul, Yilmaz Ege Filippini, Leo Oh, Junghoon Kuttappa, Ragh Lerner, Scott Kaneko, Mineo Taskin, Baris Drexel Univ Philadelphia PA 19104 USA Japart Adv Inst Sci & technol Tokyo Japan

ISBN: (纸本)9798350330991;9798350331004

This paper introduces a novel design automation methodology for charge recovery logic (CRL). The proposed methodology combines a novel logic compression algorithm with automatic schematic generation to automate the design process of CRL, enabling power and performance simulations for a large number and variety of CRL circuits. As a measure of the effectiveness of the proposed design flow, automated implementations of CRL equivalents of the LGSynth'91 combinational benchmark circuits are compared with their CMOS counterparts. The results demonstrate a trade-off in power for area: Automatically generated CRL circuits dissipate 51.3% less power on average compared to CMOS equivalents, occupying 54.9% larger area.

关键词： Low-power Charge Recovery Logic Adiabatic ogic electronic design Automation

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Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation

Enhancing ML model accuracy for Digital VLSI circuits using ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Srivastava, Prasha Kumar, Pawan Abbas, Zia Int Inst Informat Technol Hyderabad India

ISBN: (纸本)9798350330991;9798350331004

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in artificial data generation for electronic circuits to enhance the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion models to real data. We validate the quality of generated data and demonstrate that data augmentation is certainly effective in the predictive analysis of VLSI design for digital circuits.

关键词： Diffusion models Artificial data generation design and testing Digital circuits

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Functional Verification of Arithmetic circuits: Survey of Formal Methods 25

Functional Verification of Arithmetic Circuits: Survey of Fo...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ciesielski, Maciej Yasin, Atif Dasari, Jiteshri Univ Massachusetts Amherst MA 01003 USA

ISBN: (纸本)9781665494311

This paper gives a brief survey of current stateof-the-art techniques for formal verification of arithmetic circuits with suggestions for future work. In contrast to standard BDD or SAT-based approach that require a reference circuit it concentrates on Symbolic Computer Algebra (SCA) and related techniques that verify the circuits w.r.t. its abstract arithmetic specification. We examine the original computer algebra method;review the algebraic techniques of forward and backward rewriting;and AIG rewriting. We also propose a "hardware rewriting" method, which replaces algebraic rewriting by hardware synthesis of the circuit under verification appended with an inverse of the circuit, expecting it to be reduced to a redundant one.

关键词： Algebra Hardware Standards electronic circuits Arithmetic Formal verification

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Conure: Surrogate-based Artwork Generator for RFCMOS Integrated Inductors

Conure: Surrogate-based Artwork Generator for RFCMOS Integra...

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ieee International symposium on circuits and systems (ISCAS)

作者： Rahman, Habibur Recha, Adrian Llop Fasciani, Stefano Hogganvik, Pal Gunnar Kjelgard, Kristian G. Wisland, Dag Trygve Univ Oslo Dept Informat Oslo Norway Univ Oslo Dept Musicol Oslo Norway

ISBN: (纸本)9798350330991;9798350331004

designing integrated inductors can be a resourceintensive task, requiring computationally demanding electromagnetic simulations and relying on libraries constrained by the capabilities offered by foundries. In this paper, we present a surrogate-based artwork generator for integrated inductor design: Conure. The surrogate model is based on a single artificial neural network that predicts the inductor's performance over a frequency range of 1MHz to 50GHz from geometric parameters. It is capable of processing diverse coil configurations for the entire frequency range in a single model. Additionally, the optimization algorithm NSGA-II has been applied to derive design parameters that meet desired specifications. Conure is a promising approach for complete CMOS RF passive component design. The presented model is trained using data from electromagnetic simulations of coplanar symmetric octagonal inductors in 65nm CMOS. However, Conure can be scaled to other processes, inductor geometries, and frequencies.

关键词： electronic design automation RF CMOS inductor surrogate model machine learning artificial neural network optimization NSGA-II

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Correlation Power Analysis of SipHash 25

Correlation Power Analysis of SipHash

引用

25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Oleksak, Matus Miskovsky, Vojtech Czech Tech Univ Dept Digital Design Fac Informat Technol Prague Czech Republic

ISBN: (纸本)9781665494311

SipHash is ARX-based pseudorandom function optimized for short inputs. It was developed as a hash table lookup function, but it is also used for MAC generation. At the time of writing, there was no side-channel attack on SipHash known to us. This work is about application of CPA attack on SipHash. Attack was performed on ChipWhisperer CW308 UFO Board with STM32F0 target. Approximately 800 power traces were needed for succesful attack. Leakage information from XOR was used to attack cipher key. The main contribution of this work is power model of binary addition including carry propagation.

关键词： CPA SipHash ARX side-channel Chipwhisperer

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Virtual Prototype driven design, Implementation and Evaluation of RISC-V Instruction Set Extensions 25

Virtual Prototype driven Design, Implementation and Evaluati...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Funck, Milan Herdt, Vladimir Drechsler, Rolf DFKI GmbH Cyber Phys Syst D-28359 Bremen Germany Univ Bremen Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9781665494311

RISC-V is a modern open source Instruction Set Architecture (ISA) and designed in a very extendable manner, which allows for highly application specific solutions. However, the identification of suitable instruction set extensions usually requires a significant manual effort and therefore is a very challenging process. In this paper we propose a lightweight alternative methodology to find suitable application-specific RISC-V extensions, using a Virtual Prototype (VP). This is done, purely by observing the used instructions during the execution of the targeted application on the VP. Therefore, no further information about the application itself are needed. In this context the advantages and the flexibility of a VP and the straightforward extendability of the RISC-V ISA are demonstrated.

关键词： Instruction sets Prototypes Manuals electronic circuits

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