This paper presents a design of a 16-bit pipeline ALU. The ALU is implemented by using a novel asynchronous pipeline architecture. The architecture has simple handshake cells and these cells are embedded in the pipeli...
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This paper presents a design of a 16-bit pipeline ALU. The ALU is implemented by using a novel asynchronous pipeline architecture. The architecture has simple handshake cells and these cells are embedded in the pipeline stage as normal logic cells. As a result, the speed of the ALU can be very fast.
In this paper an alternative approach is given for implementing a fixed template cellular nonlinear network processor. The new concept is based on calculations in the digital domain to achieve accuracy not easily avai...
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In this paper an alternative approach is given for implementing a fixed template cellular nonlinear network processor. The new concept is based on calculations in the digital domain to achieve accuracy not easily available with analog circuitry. A particular task, namely a noise removal operation, is considered here. Simplifications to the integration update rule are introduced that make the hardware realization simple. Moreover, results are given where the number of iteration steps in the integration show the achieved accuracy in the processed image with different word lengths. The design of the processor cell is given in a block level and both the processing time and the size of the hardware realization of this topology are estimated.
作者:
D. ProtheroeF. PessolanoSchool of Electrical
Electronic & Information EngineeringCentre for Concurrent Systems South Bank University London UK School of Computing
Information Systems & MathematicsCentre for Concurrent Systems South Bank University London UK
This paper proposes a method for defining the quality of a digital system in terms of measurable parameters of both the specification and a subsequent implementation of the design. Initially, software quality metrics ...
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This paper proposes a method for defining the quality of a digital system in terms of measurable parameters of both the specification and a subsequent implementation of the design. Initially, software quality metrics are reviewed together with their application to hardware description languages. Metrics relating to circuit implementations are then discussed, such as device and testing costs, reliability, etc. A set of metrics are then proposed and evaluated for a range of VHDL specifications and the circuits resulting from logic synthesis. Initial results indicate that there is a strong correlation between specification and circuit metrics, so that their ratio may be used as a measure of design quality. Further work is proposed in order to validate the measure over a larger number of examples.
In this paper, an application of a simplified second-order lattice-based adaptive IIR notch filter to binary FSK demodulation is presented. The design method and performance evaluation of the demodulator, based on mea...
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In this paper, an application of a simplified second-order lattice-based adaptive IIR notch filter to binary FSK demodulation is presented. The design method and performance evaluation of the demodulator, based on mean-squared error analysis of the steady-state variable coefficient fluctuations of the adaptive notch filter are studied. Derived analytical results are compared with computer simulation results for confirmation.
This paper presents a full-custom building-block layout generation system that substantially improves the process of analog IC design automation. The tool generates layout for primitive devices and building blocks. An...
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This paper presents a full-custom building-block layout generation system that substantially improves the process of analog IC design automation. The tool generates layout for primitive devices and building blocks. Analog functional blocks are recognised by a set of knowledge rules and are extracted in a block-level netlist. The novel system architecture involves both "hard and "soft" sets of data in the generation phase, and achieves very significant savings in run time. The system's capability to improve analog layout quality is demonstrated through example results.
In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; ...
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In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic approach for the generation and evaluation of synthetic benchmark circuits is presented. A number of existing benchmark generation methods are examined using direct validation of size and topological parameters. This exposes certain features and drawbacks of the different methods.
This paper proposes a design methodology for transitional low-pass filters using six classical approximations of polynomial filters. The design is achieved taking into account a prescribed specification, leading to a ...
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This paper proposes a design methodology for transitional low-pass filters using six classical approximations of polynomial filters. The design is achieved taking into account a prescribed specification, leading to a better trade-off among the magnitude, phase and/or time responses. With this approach it is possible to design filters that have an improved performance than those designed with classical polynomial approximations or some other transitional filters proposed in the literature. An example demonstrating the results and effectiveness of our proposal is presented.
The idea of using FET, especially CMOS, circuitry to implement circuits similar to log domain filters is explored. Using ideas similar to those employed in the creation of log domain filters, an approximation leads to...
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The idea of using FET, especially CMOS, circuitry to implement circuits similar to log domain filters is explored. Using ideas similar to those employed in the creation of log domain filters, an approximation leads to the development of "C-log domain" filters. The synthesis of such filters is explored and two design examples are given.
An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constr...
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An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.
The performance of integrated inductors is quantified, with respect to geometrical parameters and silicon process characteristics. A custom EDA tool is employed for modeling and simulating an assortment of inductor to...
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The performance of integrated inductors is quantified, with respect to geometrical parameters and silicon process characteristics. A custom EDA tool is employed for modeling and simulating an assortment of inductor topologies under various process schemes. The aim is to outline inductor performance limits, mainly in terms of inductance, quality factor and resonant frequency. Also, guidelines are provided for their optimal physical design and for process enhancements that may benefit their performance in RF ICs.
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