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Fuzzy reasoning for the design of CNN-based image processing systems

Fuzzy reasoning for the design of CNN-based image processing...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M. Balsi F. Voci Department of Electronic Engineering University of Roma La Sapienza Rome Italy

Fuzzy reasoning in image processing has been proved to be a very effective way to formalize complex inference techniques based on heuristics or experience, taking perceptual quality criteria into account. In this paper, we discuss implementation of fuzzy reasoning image processing on the standard cellular neural network universal machine. In this way, it is possible to employ such powerful massively parallel chips to speed up use of known algorithms, and to systematize design of new perceptual-quality driven CNN applications.

关键词： Fuzzy reasoning Image processing Cellular neural networks Signal processing algorithms Fuzzy logic Turing machines Algorithm design and analysis HTML Boolean algebra Pixel

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A high-speed single-phase-clocked CMOS priority encoder

A high-speed single-phase-clocked CMOS priority encoder

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Jinn-Shyan Wang Chun-Shing Huang Institute of Electrical Engineering National Chung Cheng University Chiayi Taiwan

ISBN: (纸本)0780354826

The maximum operating frequency of a priority encoder is usually limited by the long propagation delay of the priority token, and the delay will increase as the number of bit of the priority encoder increases. The concept of look-ahead can be applied to improve the performance. In this paper, the design of a high-speed priority encoder is presented. The main idea of this new design is a multi-level look-ahead structure, which can be realized efficiently by the single-phase-clocked dynamic CMOS logic. A 32-bit priority encoder is implemented in a 3 V, 0.6 /spl mu/m CMOS technology to evaluate the performance of proposed techniques. The new priority encoder uses a 3-level look-ahead structure. As compared with the conventional design, the new design achieves 57% speed improvement with 5% layout area reduction.

关键词： CMOS logic circuits Propagation delay Signal design Frequency Logic design CMOS technology Voltage Clocks Logic circuits electronic mail

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A partial scan design by unifying structural analysis and testabilities

A partial scan design by unifying structural analysis and te...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： J. Park S. Shin S. Park Appeal Telecom South Korea Samsung Electronics Company Limited South Korea Department of Computer Science and Engineering Hanyang University South Korea

To overcome the large extra hardware overhead attendant in the full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. In this paper we analyzed and unified the strength of the techniques by structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flops but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for the most ISCAS89 benchmark circuits.

关键词： Circuit testing Circuit faults Sequential analysis electronic equipment testing Flip-flops Controllability Hardware Sequential circuits Feedback Observability

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An application of Verilog-A to modeling of back propagation algorithm in neural networks

An application of Verilog-A to modeling of back propagation ...

引用

Midwest symposium on circuits and systems (MWSCAS)

作者： K. Suzuki A. Nishio A. Kamo T. Watanabe H. Asai Department of Systems Engineering Faculty of Eng. Shizuoka University Hamamatsu Japan School of Administration and informatics University of Shizuoka Hamamatsu Japan

This paper describes an application of the Verilog-A, which is a hardware description language for analog applications, to the modeling of neural networks. We attempt to simulate neural networks having a learning algorithm, which has not been designed with electronic circuits. The learning algorithm is modeled with Verilog-A and the suitable synaptic weights are solved by Verilog-A simulation.

关键词： Hardware design languages Intelligent networks Neural networks Circuit simulation Modeling electronic circuits Very large scale integration Digital systems Circuit synthesis Neurons

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Direct digital tuning for continuous-time filters

Direct digital tuning for continuous-time filters

引用

Midwest symposium on circuits and systems (MWSCAS)

作者： T. Salo S. Lindfors K. Halonen Electronic Circuit Design Laboratory Helsinki University of Technology Finland

Direct tuning techniques of continuous-time filters for mobile radio receivers are discussed. Different design aspects and the effect of nonidealities are considered. A single-shot tuning scheme which is based on digital control word calculation algorithm is proposed for cases (CDMA) where sufficient time cannot be allocated for feedback based tuning as in time-division multiplexed radio systems (TDMA).

关键词： Digital filters Circuit optimization Tuning Master-slave Receivers Signal processing Frequency response Tuned circuits Feedback circuits Feedback loop

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A hybrid genetic algorithm method for optimizing analog circuits

A hybrid genetic algorithm method for optimizing analog circ...

引用

Midwest symposium on circuits and systems (MWSCAS)

作者： S. Papadopoulos R.J. Mack R.E. Massara Department of Electronic Systems Engineering University of Essex Colchester UK

An approach is presented for the automated sizing of analog circuits based upon a combination of a genetic algorithm (GA) with a least squares (Gauss-Newton) gradient search. The method combines the global-search properties of the GA with the fast local convergence properties of the least squares method to produce a circuit design from random initial component values in a reduced time compared to the application of a direct GA method, or a restart least squares algorithm. Results are presented to demonstrate the application of the method in the design of both passive and active circuits.

关键词： Genetic algorithms Optimization methods Analog circuits Least squares methods Newton method Recursive estimation Convergence Circuit synthesis design methodology Active circuits

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Truncation DC-error elimination in FIR filters

Truncation DC-error elimination in FIR filters

引用

Midwest symposium on circuits and systems (MWSCAS)

作者： L. Koskinen M. Kosunen S. Lindfors K. Halonen Electronic Circuit Design Laboratory Helsinki University of Technology Finland

The truncation of binary numbers can be modeled as noise and a DC-error if certain conditions are fulfilled. These truncation effects in finite impulse response (FIR) digital filters that are realized with canonic signed-digit (CSD) representation are reviewed. Three different techniques to reduce or eliminate the DC-error are presented and compared with respect to hardware and power consumption requirements.

关键词： Finite impulse response filter Signal to noise ratio Circuit noise Energy consumption Digital filters White noise Filtering electronic circuits Laboratories Digital circuits

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A top-down methodology to accommodate circuit interaction within an analogue synthesis system

A top-down methodology to accommodate circuit interaction wi...

引用

Midwest symposium on circuits and systems (MWSCAS)

作者： D. Enright R.J. Mack R.E. Massara S. Papadopoulos P.B. Wu R.J. Binns P. Hallam Department of Electronic Systems Engineering University of Essex UK Division of Electrical and Electronic Engineering University of Northumbria UK Faculty of Engineering and Computer Technology University of Central England UK

This paper describes a methodology for designing analog systems starting from a top-level, behavioral model. The methodology has been incorporated within an analog synthesis system (ADSA), which is based upon the use of optimization at both behavioral and circuit levels. Initial design uses ideal models without interaction. Model refinement takes place to accommodate, first, signal offsets and levels, and then, the source and load impedances of the circuit blocks. An example is given of the methodology applied to the design of a Downconverter.

关键词： Circuit synthesis design methodology Process design design optimization design engineering systems engineering and theory Impedance Analog computers Signal synthesis Optimization methods

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Parallel symbolic sensitivity analysis of large-scale linear analogue circuits

Parallel symbolic sensitivity analysis of large-scale linear...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： F. Eberhardt W. Tenten P.R. Shepherd Bosch Microelectronics Reutlingen Germany Department of Electronic Electrical Engineering University of Bath Bath UK

This paper presents a new effective method for symbolic sensitivity analysis of large scale analogue circuits. Based on the "sequence of expressions" (SOE) approach the sensitivities with respect to all parameters are calculated in parallel. Experimental results show that a significant acceleration compared to previously described symbolic procedures is achieved and that the method can be faster than the numerical adjoint approach.

关键词： Sensitivity analysis Large-scale systems Frequency Acceleration Microelectronics Process design Transfer functions Iterative methods Circuit optimization Tolerance analysis

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design of multilayer discrete time cellular neural networks for image processing tasks based on genetic algorithms

Design of multilayer discrete time cellular neural networks ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： F. Lopez D.L. Vilarino D. Cabello Department of Electronics and Computer Science University of Santiago de Compostela Spain Universidade de Santiago de Compostela Santiago de Compostela Galicia ES

Genetic algorithms are applied to design multilayer discrete-time cellular neural networks for image processing tasks, To this end not only the templates of the different layers will be optimized, but also the network structure itself, that is, number of layers and iterations per layer. As a difference with traditional strategies, both the definition of the optimum network size and the template optimization are done simultaneously.

关键词： Multi-layer neural network Cellular neural networks Image processing Nonhomogeneous media Genetic algorithms Algorithm design and analysis Computer science electronic mail Computer networks Computer architecture

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