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Decoupled optimization technique for design of switching regulators using genetic algorithms

Decoupled optimization technique for design of switching reg...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： J. Zhang H. Chung W.L. Lo S.Y.R. Hui A. Wu Department of Electronic Engineering City University of Hong Kong Kowloon Hong Kong China

This paper presents a decoupled optimization technique for design of switching regulators using genetic algorithms (GA). The optimization entails selection of the component values in the regulator to meet some static and dynamic requirements. During the optimization, a regulator is decoupled into two parts, including the power conversion stage (PCS) and the feedback network (FN). The PCS is optimized with the required static characteristics, while the FN is optimized with the required static and dynamic characteristics of the whole system during disturbances. The proposed technique is illustrated with the design of a buck regulator. Predicted results are compared to the available literature and are verified with experimental measurements.

关键词： design optimization Algorithm design and analysis Regulators Genetic algorithms Personal communication networks circuits Power electronics Optimized production technology Stochastic processes Biological cells

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A quantitative method for evaluating the quality of analog layout

A quantitative method for evaluating the quality of analog l...

引用

Midwest symposium on circuits and systems (MWSCAS)

作者： P.B. Wu R.J. Mack R.E. Massara Department of Electronic Systems Engineering University of Essex Colchester UK

A quantitative benchmarking metric is presented for the objective evaluation of the quality of analog layout. It facilitates comparisons between alternative design automation tools, and, for a given tool, provides the assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net-routing optimality. The results demonstrate the effectiveness of the metric in that the calculated scores provide a characterization that corresponds to expert designers' judgements.

关键词： Routing design automation Performance evaluation Costs Q measurement systems engineering and theory Mobile communication Fabrication Integrated circuit interconnections Predictive models

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design of a cellular nonlinear network for analogue simulation of reaction-diffusion PDEs

Design of a cellular nonlinear network for analogue simulati...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： V. Bonaiuto A. Maffucci G. Miano M. Salerno F. Sargeni C. Visone Dipartimento di Ingegneria Elettrica Università di Roma Tor Vergata Rome Italy Dipartimento di Ingegneria Elettronica Università di Napoli Federico II Rome Italy

In this paper an electronic circuit for the analogue simulation of different finite dimensional approximations of the nonlinear reaction diffusion equation is proposed. The circuit consists of an array of nonlinear cells similar to the Cellular Neural Networks already stated and hardware implementation of each cell is controlled by two independent parameters and uses current mode circuitry. The final purpose of these investigations is to get a better insight on the possibility of analogue simulation of nonlinear evolutive partial differential equations by means of these circuits.

关键词： Cellular networks Steady-state Nonlinear equations Circuit simulation Partial differential equations Differential equations Piecewise linear approximation Finite difference methods Land mobile radio cellular systems electronic circuits

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VLSI implementation of GRBF (Gaussian radial basis function) networks

VLSI implementation of GRBF (Gaussian radial basis function)...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： I.C. Cevikhas A.S. Ogrenci G. Dundar S. Balkur Res. Center TUBITAK Marmara Turkey Electronics Engineering Department Kadir Has University Istanbul Turkey Electrical and Electronic Engineering Department Bogazici University Istanbul Turkey

A GRBF network is designed for VLSI implementation. Building blocks of the network consist mainly of analog circuits: op amp, multiplier, multiplying DAC (digital to analog converter), floating resistor, summer and exponentiator. Parameters of the network (center, width of the Gaussian function and output layer weights) are represented digitally for convenient interfacing. It is shown that individual GRBF units allow independent tuning of center, width and amplitude. Several network structures are simulated as function approximation examples, and the performance is verified to be satisfactory.

关键词： Very large scale integration Neural networks Computer networks Adders Function approximation Neural network hardware Tuned circuits Councils electronic mail design engineering

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Convergence and steady-state analysis of the cost function adaptation algorithms for data echo cancellation

Convergence and steady-state analysis of the cost function a...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： C. Rusu C.F.N. Cowan Signal Processing Laboratory Digital Media Institute Tampere University of Technology Tampere Finland Department of Electrical and Electronic Engineering Queen''s University Belfast Belfast UK

A general convergence and steady-state analysis of the recently proposed cost function adaptation algorithms is carried out in this paper, and closed-form expressions for the step-size bounds, time-constants and misad... 详细信息

关键词： Convergence Steady-state Algorithm design and analysis Cost function Signal processing algorithms Least squares approximation Echo cancellers Stochastic processes Error correction Equations

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Optimum Laguerre filter design technique for sigma-delta demodulators

Optimum Laguerre filter design technique for sigma-delta dem...

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ieee International symposium on circuits and systems (ISCAS)

作者： S.S. Abeysekera Xue Yao School of Electrical and Electronic Engineering Nanyang Technological University Singapore

As an alternative to conventional FIR filters, an optimal IIR filter architecture based on orthonormal Laguerre functions is proposed for Sigma-Delta (/spl Sigma/-/spl Delta/) demodulators. A Laguerre IIR filter design methodology is presented via the optimization of a quadratic function subject to a linear and a quadratic constraint. An efficient procedure to perform the optimization is discussed. The proposed IIR filter is easy to implement because it needs only a small number of components and therefore well suited for VLSI implementations. The impact of the selection of filter pole on the filter stability and phase linearity is discussed. The robustness issue of the Laguerre IIR filter is also addressed.

关键词： Delta-sigma modulation IIR filters Finite impulse response filter Demodulation design methodology Constraint optimization design optimization Very large scale integration Stability Linearity

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design of CMOS composite transistors with improved operating region

Design of CMOS composite transistors with improved operating...

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Midwest symposium on circuits and systems (MWSCAS)

作者： Young-Gyu Yu Seok-Woo Choi Dong-Yong Kim Kyu-Tae Park Hong-Jo Ahn Faculty of Electronic and Information Engineering Chonbuk National University Chonju South Korea Electrical Circuits and Systems Research Institute Chonbuk National University Chonju South Korea Korea Research Council for Industrial Science and Technology Seoul South Korea Dept. of Electrical Engineering The Ohio State University Columbus OH USA

Proposes two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistors 1 and 2 employ a p-type folded composite transistor and an electronic Zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried out using 0.25/spl mu/m n-well process with 2.5V supply voltage.

关键词： Threshold voltage Diodes circuits and systems Circuit simulation Low voltage Analog circuits Breakdown voltage Signal processing Transconductance MOS devices

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New metrics for architectural level power performance evaluation

New metrics for architectural level power performance evalua...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Lihong Jia Yonghong Gao Tenhunen Electronic System Design Laboratory Royal Institute of Technology Sweden

ISBN: (纸本)0780354826

In this paper, we present new metrics to evaluate the performance of VLSI circuits with regards to the power consumption in the architectural level from the system point of view. One advantage of the new metrics is that the metrics not only calculate the power consumption itself but also evaluate the "low power possibility" of the architectures from the system point of view; another advantage is that the metrics consider the effects of the process technology and it can be used to evaluate the power consumption performance in the future advanced VLSI technology. Specially, we point out that reducing power supply voltage to reduce the power consumption will become less and less efficient in the deep submicron regime and thus the architecture-driven voltage scaling low power design approach will not work as well as in the previous technology.

关键词： Energy consumption Power supplies Throughput circuits Very large scale integration Laboratories Low voltage Costs Silicon System performance

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design of a low-voltage, low-power, wide-tuning integrated oscillator

Design of a low-voltage, low-power, wide-tuning integrated o...

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ieee International symposium on circuits and systems (ISCAS)

作者： T.Y.K. Lin A.J. Payne Department of Electrical and Electronic Engineering Integrated Circuits and Systems Research Group Imperial College of Science Technology and Medicine London UK

This paper presents the design of a low-voltage, low-power, wide-tuning, monolithic voltage-controlled oscillator (VCO). The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel low-voltage, high performance active inductor. It operates in the 1.1 GHz to 2.1 GHz frequency range while consuming 1 mA from a 2.5 V power supply, with scope for further reduction to 1 V. The VCO's phase noise level is -83 dBc/Hz at 600 kHz offset from a 1.5 GHz carrier with a Q of 7 and can be further reduced to -88 dBc/Hz at 600 kHz offset from a 2.5 GHz carrier if the Q is increased to 24.

关键词： Voltage-controlled oscillators Active inductors Phase noise Circuit optimization Circuit topology Phase locked loops Gyrators Impedance Voltage Monolithic integrated circuits

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Enhancing dynamic range in differential log-domain filters based on the two-filters approach

Enhancing dynamic range in differential log-domain filters b...

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ieee International symposium on circuits and systems (ISCAS)

作者： R.M. Fox Department of Electrical & Computer Engineering University of Florida Gainesville FL USA

The "two filter" method for designing differential log-domain filters does not allow true class AB operation of filters having complex poles. However, differential log-domain filter structures that pass DC offsets from the input current splitter to each internal state variable can operate linearly to fairly high output modulation indices. New low-V/sub DD/ translinear current-splitter circuits are presented, including a harmonic-mean splitter, which produces increased DC offsets compared to geometric-mean circuits. The increased offsets are shown to allow significant increases in the range of indiscrete signals in differential log-domain filters with appropriate structures.

关键词： Dynamic range Band pass filters Matched filters Transfer functions design engineering electronic mail design methodology Filtering Tunable circuits and devices Transconductance

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