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Innovative Median Finding Algorithm for Coherent Noise Removal in High Energy Physics Experiments 16

Innovative Median Finding Algorithm for Coherent Noise Remov...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Guimaraes, Nicolas Aniya, Guilherme Sanches, Bruno Mandjavidze, Irakli Neyret, Damien Van Noije, Wilhelmus Department of Electronic Systems Engineering São Paulo Brazil Irfu Cea Gif-Sur-Yvette France

ISBN: (纸本)9798331522124

Several high energy physics experiments suffer from coherent noise affecting their readout electronics. To solve that, the highly successful SAMPA chip is gaining a new successor, the SALSA front-end readout ASIC, which is going to be used in the EIC experiment of the Brookhaven National Laboratory, United States. This new integrated circuit is going to have a common mode noise subtraction, a non-linear filter that is based on finding median values between the many channels of the chip. To guarantee peak efficiency in the filter implementation, this work focuses on the filter's core: the median finder. This part needs to have an efficient algorithm to be implemented in hardware, therefore this paper shows three approaches, two of which are original techniques for digital median finding. These three designs were implemented and verified in TSMC 65nm technology and lastly they were compared in terms of speed, area, power consumption and a preliminary evaluation of error tolerance. © 2025 ieee.

关键词： Electron emission

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Study of an OPTO-ASIC for a Functionally Safe Speed Sensor Using the Spatial Frequency Filter Method

Study of an OPTO-ASIC for a Functionally Safe Speed Sensor U...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Frank Wasinski Werner Bonath Ubbo Ricklefs Michael Schwarz Josef Börcsök Dept. of Electrical Engineering and Information Technology THM University of Applied Sciences Giessen Germany ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

For decades, speed sensors based on the spatial frequency filter method have successfully proven themselves in a wide range of applications. This makes the sensor concept particularly suitable for the area of functional safety. New filter variants extend the previous measuring range to very low speeds up to standstill detection. By combining the sensor with a safety system on chip for recording and analysing measured values, a functionally safe measuring chain can be established. In order to demonstrate the variability and performance of the new filters, an optical application-specific integrated circuit was designed, which forms the basis for further extensive tests. The core components are a large number of freely configurable photodiode channels, which were realised via a redundant structure, as well as two different transimpedance amplifier concepts. In the further course of the project, the ASIC will be analysed with regard to its desired performance parameters and its robustness.

关键词： Optical filters Semiconductor device measurement Optical design Stimulated emission Safety Topology System-on-chip Optical sensors Optical amplifiers Velocity measurement

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River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars

River: Sneak Path Aware READ-based In-Memory Computing for 1...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Till Schnittka Chandan Kumar Jha Sallar Ahmadi-Pour Rolf Drechsler University of Bremen Bremen Germany DFKI GmbH Bremen Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In-memory Computing (IMC) using emerging devices has shown immense potential. Among these devices, memristors have emerged as one of the most popular for performing digital IMC. While several methods exist for digital IMC using memristors, most require expensive write operations in terms of energy, latency, and endurance. Hence, READ-based IMC techniques have been proposed to reduce the number of writes to the memristor crossbar. However, existing techniques rely on simple gates that can be mapped to the memristive crossbar, making them non-optimal, and they suffer from unwanted sneak paths causing undesired behavior. In this work, we alleviate these limitations and propose an optimized synthesis methodology for 1T1M crossbars called RIVER. RIVER supports more complex gates and is sneak-path aware. When comparing RIVER with the state-of-the-art using ISCAS’ 85 and EPFL benchmarks, we achieve 33% less gate utilization on average while reducing the average staircase length by 37%. Moreover, these enhancements result in a 58% reduction in the required crossbar area. After eliminating sneak paths, RIVER still shows 38% less area usage on average as compared to the state-of-the-art.

关键词： Performance evaluation Memristors Logic gates Benchmark testing In-memory computing Rivers electronic circuits

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Towards an Automated Debugging Approach for Fault Identification in Quantum circuits

Towards an Automated Debugging Approach for Fault Identifica...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Anton Maidl Abhoy Kole Kamalika Datta Jannis Stoppe Rolf Drechsler Institute for the Protection of Maritime Infrastructure German Aerospace Center (DLR e.V.) Bremerhaven Germany Institute of Computer Science University of Bremen Bremen Germany Cyber-Physical Systems DFKI GmbH Bremen Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

In this paper, we propose a novel method for locating and diagnosing bugs in quantum circuits. Debugging in the quantum domain is especially challenging due to the inherent inability of assessing the quantum state of a program. Moreover, explaining the root cause behind unexpected outcomes is hard due to the limited information gain provided by measurements. Our approach aims to address both of these issue: Firstly, the bug site is identified using a standard circuit slicing technique combined with an associated measurement strategy. Secondly, we provide information about the nature of the bug, generated through repeated measurements. To minimize the number of measurements, we introduce a notion of equivalence classes based on unitary operations. This allows us to partition the gate library into classes that produce indistinguishable results under certain measurements. Finally, We assess the effectiveness and measurement complexity of our method by applying it to relevant primitive gate components and well-known quantum algorithms. Our empirical results shows that in 95.79% of all cases, our approach reveals the correct location of the bug along with a valid set of fault candidates. Furthermore, we demonstrate that the required number of circuit executions scales logarithmically with the circuit depth or linearly with the number of qubits.

关键词： Accuracy Computer bugs Qubit Debugging Logic gates Search problems Libraries Circuit faults Quantum circuit Standards

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Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design

Ultra-Thin-Body and Buried Oxide FD-SOI next generation node...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Claire Fenouillet-Beranger Laurent Fesquet Rihab Chouk Gabriel Pares Baudoin Martineau Marie-Claire Cyrille Thierry Poiroux Olivier Billoint Dominique Noguet CEA-Leti Univ. Grenoble Alpes Grenoble France CNRS Grenoble INP TIMA Université Grenoble Alpes Grenoble France

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

The European FAMES Pilot Line addresses a set of technologies including fully depleted silicon-on-insulator technology advanced nodes and embedded non-volatile memories. This paper addresses these two technologies and the programs planned to help designers to use these technologies at their best. The specific electrical properties of FD-SOI devices, are discussed, both in terms of transistor modelling and process highlighting the levers exploited to boost the performance of the future 10-7nm nodes will be also highlighted. The paper also address embedded Non-Volatile Memory (eNVM) devices integrated in the BEOL of advanced FD-SOI CMOS technologies with the aim to open opportunities for disruptive IC architectures and designs using the most appropriate eNVM for the considered applications. OxRAM, FeRAM, BEOL FeFET and MRAM are addressed in FAMES and in the paper and potential new applications are discussed. Finally, the way these technologies are provided to designers through training programs is described.

关键词： Training Hands Nonvolatile memory Ferroelectric films Random access memory Europe Silicon-on-insulator Transistors FeFETs Strain

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design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-compute...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Hussien Abdo Jan Lappas Mohammadreza Esmaeilpour Christian Weis Norbert Wehn University of Kaiserslautern-Landau (RPTU) Germany

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

High-speed memory interfaces require the design of optimised low-power and robust analog circuits. This poses significant challenges in sizing due to the inability of using complex modern transistor models, such as the Berkeley Shortchannel IGFET Model (BSIM), to calculate the sizing of the circuits based on hand-analysis. This forces designers to perform iterative simulations, which is time-intensive and error-prone. To address these issues, this work presents an automated sizing approach using pre-computed lookup tables (LUTs) for a 4.3 Gb/s LPDDR4X transceiver in 12nm FinFET technology. The receiver is designed based on g m /I D sizing methodology where look-up tables are used to compute a set of matrices representing the possible design points based on the circuit topology. The design space is constrained by the biasing level, gain, and bandwidth to find an optimised design point in terms of operation region, speed and power. The driver circuit design is automated based on a new algorithm which computes the estimated ON-resistance from the look up table and finds an optimum sizing which fulfills the required impedance range. The calculated sizing of the proposed design approach was used as an input for spectre simulator to compare the simulation results with the input specifications, showing an error margin of less than 1%. Furthermore, the receiver power consumption was evaluated to be 70% less than the work in literature. The proposed driver topology, which uses low voltage swing terminated logic (LVSTL) and near-ground signaling (NGS), provides a 38−120Ω impedance range at all process, voltage and temperature variations (PVT) for the postlayout results and consumes relatively low power when compared to literature.

关键词： Power demand Simulation Receivers Voltage FinFETs Transceivers Table lookup Topology Impedance Transistors

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A 22nm CMOS PFM Buck Converter Used in a 32-Bit RISC-V Microcontroller for IoT Applications 16

A 22nm CMOS PFM Buck Converter Used in a 32-Bit RISC-V Micro...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Oliveira, Luiz H. N. Amaral, Wellington A. Haddad, Sandro A. P. Munoz, Daniel M. Barcelos, Eduardo A. Sotero, Vinicius V. M. Jonhson, Emmanuel K. M. Campagnucci, Pamela R. A. N. Lima, Luis V. N. Electronics Engineering Undergraduate Program Faculty of Gama Brazil Mechatronics Graduate Program University of Brasilia Faculty of Technology Department of Mechanical Engineering DF Brasilia Brazil

ISBN: (纸本)9798331522124

The demand for efficient power management solutions in electronic devices has increased significantly, especially for microcontrollers operating in low-power modes. This article presents the design and implementation of a Pulse Frequency Modulation (PFM)-based buck converter for applications in 32-bit microcontrollers using 22nm CMOS technology. The methodology involves the development of a Constant On Time (COT) architecture that maintains a fixed duration for the activation of the high-side MOSFET, using a monostable multivibrator to generate the necessary timing signals. The converter's performance was simulated under various load conditions and process corners to evaluate its efficiency and output characteristics. The results show that the proposed buck converter achieves high efficiency, with peak values above 95%, while maintaining a low output ripple. Specifically, the converter exhibits an efficiency of 93.4% at a load of 1mA, with output ripple voltages as low as 2.20 mV under ideal conditions. The contributions of this work lie in the advancement of PFM converter technology for modern microcontroller applications, demonstrating the potential of 22nm CMOS processes to improve power efficiency and performance. © 2025 ieee.

关键词： CMOS integrated circuits

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Automatic generation of input-aware approximate arithmetic circuits

Automatic generation of input-aware approximate arithmetic c...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Mario Barbareschi Salvatore Barone Alberto Bosio Bastien Deveautour Ali Piri Marcello Traiola Department of Electrical Engineering and Information Technologies University of Naples Federico II Naples Italy Department of Computer Science and Technologies Pegaso Digital University Naples Italy CNRS UCBL CPE Lyon INL UMR5270 Univ Lyon ECL INSA Lyon Ecully France CNRS IETR-UMR 6164 Nantes Université Nantes France CNRS Inria IRISA - UMR 6074 Univ Rennes Rennes France

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Approximate Computing (AxC) is systematically applied across various abstraction levels to reduce overheads and enhance the performance of applications such as image processing and machine learning. However, AxC does not typically consider the specific workload (i.e., data input) of a given application. For instance, in signal processing applications like filters, some inputs are constants (filter coefficients), which allows for an additional level of approximation by considering the specific input distribution. This method is known as "Input-Aware Approximation" (IAA) and has shown potential advantages in previous studies. Unfortunately, existing input-aware design methodologies lack scalability as they mostly depend on ad-hoc, non-automatic design approaches, limiting their applicability. In this paper, we investigate how the input-aware approximate design approach can be integrated into a systematic, generic, and automatic design flow. We employ state-of-the-art approximation and multi-objective optimization techniques to achieve inputawareness. Our experimental results, focusing on classical signal processing applications like FIR filters, demonstrate that the input-aware approach can provide significant savings in both area and power consumption.

关键词： Systematics Filters Power demand Philosophical considerations Finite impulse response filters Scalability Approximate computing Hardware Optimization Arithmetic

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Proceedings - 2017 ieee 20th International symposium on design and diagnostics of electronic Circuit and systems, DDECS 2017

Proceedings - 2017 IEEE 20th International Symposium on Desi...

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20th ieee International symposium on design and diagnostics of electronic Circuit and systems, DDECS 2017

ISBN: (纸本)9781538604717

The proceedings contain 37 papers. The topics discussed include: an efficient physical design of fully-testable BDD-based circuits;improving combinational circuit resilience against soft errors via selective resource allocation;mapping abstract and concrete hardware models for design understanding;Mealy-To-Moore transformation;towards approximation during test of integrated circuits;fault detection and self repair in Hsiao-code FEC circuits;fro m online fault detection to fault management in network-on-chips: a ground-up approach;logic testing with test-per-clock pattern loading and improved diagnostic abilities;an analysis of the operation and SET robustness of a CMOS pulse stretching circuit;and analog front-end for precise human body temperature measurement.

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International symposium on design and diagnostics of electronic circuits and systems

International Symposium on Design and Diagnostics of Electro...

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ieee International Test Conference (ITC)

作者： Stamenkovic, Zoran Bosio, Alberto Cserey, Gyorgy Novak, Ondrej Pleskacz, Witold Sekanina, Lukas Steininger, Andreas Stojanovic, Goran Stopjakova, Viera IHP Leibniz Inst Innovat Mikroelekt Frankfurt Oder Germany Ecole Cent Lyon Inst Nanotechnol Lyon Ecully France Pazmany Peter Catholic Univ Fac Informat Technol & Bion Budapest Hungary Tech Univ Liberec Fac Mechatron & Interdis Studies Liberec Czech Republic Warsaw Univ Technol Inst Microelect & Optoelect Warsaw Poland Brno Univ Technol Fac Informat Technol Brno Czech Republic Vienna Univ Technol Inst Comp Engn Vienna Austria Univ Novi Sad Fac Tech Sci Novi Sad Serbia Slovak Univ Technol Bratislava Fac Elect Engn & Informat Techn Bratislava Slovakia

ISBN: (纸本)9781728148236

The paper is a contribution to the 50th anniversary celebration of the International Test Conference (ITC) and its Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years. It covers the past, present, and future of the International symposium on design and diagnostics of electronic circuits and systems (DDECS), a symposium which belongs to prominent test technology related events initiated and supported by the ITC.

关键词： symposium DDECS electronics circuits systems

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