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ieee International symposium on circuits and systems (ISCAS)

作者： Qi, Yuanrui Gan, Zejun Ding, Jinghao Fu, Zhaoqi Gong, Mengshi Yu, Wenxin Southwest Univ Sci & Technol Mianyang Sichuan Peoples R China

ISBN: (纸本)9798350330991;9798350331004

Track assignment has become a crucial step within the physical design flow. In this work, we proposed a novel track assignment approach using gradients estimation and simulated annealing. Specifically, we formulate the overlap cost function and derive the gradients to estimate the quality of candidate positions for iroutes movement. A simulated annealer is devised to consume the gradients indication and perturb the track assignment solution from the global perspective. Experimental results show 5.15% lower overlap cost in average of all 10 benchmarks from DAC 2012 Routability-Driven Placement Contest, compared to the state-of-the-art approach NTA [1].

关键词： electronic design automation track assignment mutability simulated annealing

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Autocalibration Approach for Improving Robustness of Analog ICs 25

Autocalibration Approach for Improving Robustness of Analog ...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Maljar, David Arbet, Daniel Kovac, Martin Ondica, Robert Stopjakova, Viera Slovak Univ Technol Bratislava Inst Elect & Photon Bratislava Slovakia

ISBN: (纸本)9781665494311

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV. The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.

关键词： digital autocalibration process variations voltage reference analog design ultra-low voltage design CMOS

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Reinforcement-Learning-Based Foggy-Aware Optimal Placement Method for Analog and MixedSignal circuits

Reinforcement-Learning-Based Foggy-Aware Optimal Placement M...

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ieee International symposium on circuits and systems (ISCAS)

作者： Sadrafshari, Mirvala Dobre, Octavia Zhang, Lihong Mem Univ Newfoundland Dept Elect & Comp Engn St John NF Canada

ISBN: (纸本)9798350330991;9798350331004

Despite advancement in artificial intelligence (AI) and subsequent successful applications in a vast variety of areas, addressing progressive need in electronic design automation for high performance and fine precision remains a significant challenge. Optimal layout placement design, a notably timeconsuming task, often poses an issue to the conventional design process with an aim of maintaining high circuit performance. To mitigate this problem, in this paper we propose an AI-based optimization method to automate this process with better accuracy. We utilize a reinforcement learning (RL) method, advantage actor critic (A2C), to implement a full automation procedure for analog circuit layout design. A topological representation is employed to decrease the size of states in the optimization process. In addition, we have considered the foggy effect caused by electron-beam lithography (EBL) technology. Our simulation results demonstrate the remarkable efficacy of our approach, which can achieve 44 times smaller foggy effect variation and reduce the run time by 42 times in comparison with the analytical and another RL-based (DQN) method, without compromising the wire length and chip area minimization.

关键词： Artificial Intelligence Reinforcement Learning Machine Learning Analog layout Generation Placement

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Analyzing Multilevel Stochastic circuits using Correlation Matrices 25

Analyzing Multilevel Stochastic Circuits using Correlation M...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Hoffend, Owen Hayes, John P. Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

ISBN: (纸本)9781665494311

Stochastic computing (SC) is a digital design paradigm that foregoes the conventional binary encoding in favor of pseudo-random bitstreams. Stochastic circuits operate on the probability values of bitstreams, and often achieve low power, low area, and fault-tolerant computation. Most SC designs rely on the input bitstreams being independent or uncorrelated to obtain the best results. However, circuits have also been proposed that exploit deliberately correlated bitstreams to improve area or accuracy. In such cases, different sub-circuits may have different correlation requirements. A major barrier to multi-layer or hierarchical stochastic circuit design has been understanding how correlation propagates while meeting the correlation requirements for all its sub-circuits. In this paper, we introduce correlation matrices and extensions to probability transfer matrix (PTM) algebra to analyze complex correlation behavior, thereby alleviating the need for computationally intensive bit-wise simulation. We apply our new correlation analysis to two multi-layer SC image processing and neural network circuits and show that it helps designers to systematically reduce correlation error.

关键词： Stochastic computing signal correlation correlation matrix error analysis stochastic circuit design

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On SAT-Based Model Checking of Speed-Independent circuits 25

On SAT-Based Model Checking of Speed-Independent Circuits

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Huemer, Florian Najvirt, Robert Steininger, Andreas TU Wien Inst Comp Engn Vienna Austria

ISBN: (纸本)9781665494311

Formal verification plays an important role in the quality assurance of digital circuits. Apart from the now standard equivalence checking between design steps, functional correctness can be proven with model checking. In one approach, a Boolean satisfiability (SAT) problem describing the circuit's implementation and expected properties is generated for each of a bounded number of time steps and fed to a SAT solver. In synchronous circuits, the time steps correspond to cycles of the global clock. The execution of asynchronous, specifically speed-independent (SI) circuits, however, relies on local handshakes instead of a global time reference. This absence of a global clock requires a different approach for choosing time steps for the SAT problem. This paper presents how bounded, SAT-based model checking can be used on SI asynchronous circuits. We aim to give a general and accessible introduction to this topic, highlight the inherent computational complexity and show that setting up a basic model checker for SI circuits is possible with quite simple means, without any reliance on (expensive) commercial tools. For our reference implementation used in the provided examples we use the open source Z3 solver.

关键词： asynchronous speed-independent SAT bounded model checking

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An Automatable Approach for Small-Signal Stability Analysis of Power electronic-Based Power systems Using EMT Companion circuits

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ieee TRANSACTIONS ON POWER DELIVERY 2023年第4期38卷 2879-2890页

作者： Chindu, Vinay Kulkarni, A. M. Indian Inst Technol Dept Elect Engn Mumbai 400076 India

The increasing presence of power electronic (PE) controlled devices in power systems has widened the bandwidth of transients to be studied for grid stability. While these transients are normally studied using time-domain simulation (TDS), wide bandwidth linear time-invariant (LTI) state-space models are a useful complement to TDS for diagnostics, controller design and parametric analysis. A general automatable method to compute an LTI sampled-data model of a PE-based circuit is presented in this paper. The proposed method is based on the techniques employed in electro-magnetic-transient (EMT) programs to perform TDS of PE-based circuits. The method uses the building blocks of EMT nodal formulation such as conductance matrix of companion circuit and its LU factors computed during TDS, interpolation and chatter elimination corrections, and EMT model of the firing angle control system. The method yields a small-signal LTI sampled-data model which is amenable to eigenanalysis and is illustrated using simple PE-based circuits such as a buck converter and a grid-connected STATCOM with closed-loop control.

关键词： Electro-magnetic-transient (EMT) program small-signal analysis state-space model sampled-data model

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A design Space Exploration Framework for Memristor-Based Crossbar Architecture 25

A Design Space Exploration Framework for Memristor-Based Cro...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Barbareschi, Mario Bosio, Alberto O'Connor, Ian Fiser, Petr Traiola, Marcello Univ Naples Federico II Dept Elect Engn & Informat Technol Naples Italy Univ Lyon UMR5270 INL ECLINSA LyonCNRSUCBLCPE Lyon F-69130 Ecully France Czech Tech Univ Prague Czech Republic Univ Rennes INRIA CNRS IRISAUMR6074 Rennes France

ISBN: (纸本)9781665494311

In the literature, there are few studies describing how to implement Boolean logic functions as a memristor-based crossbar architecture and some solutions have been actually proposed targeting back-end synthesis. However, there is a lack of methodologies and tools for the synthesis automation. The main goal of this paper is to perform a design Space Exploration (DSE) in order to analyze and compare the impact of the most used optimization algorithms on a memristor-based crossbar architecture. The results carried out on 102 circuits lead us to identify the best optimization approach, in terms of area/energy/delay. The presented results can also be considered as a reference (benchmarking) for comparing future work.

关键词： Emerging Technologies Memristor crossbar design Space Exploration Boolean Functions Logic Synthesis

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Hardware Obfuscation of Digital FIR Filters 25

Hardware Obfuscation of Digital FIR Filters

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Aksoy, Levent Hepp, Alexander Baehr, Johanna Pagliarini, Samuel Tallinn Univ Technol Tallinn Estonia Tech Univ Munich Munich Germany

ISBN: (纸本)9781665494311

A finite impulse response (FIR) filter is a ubiquitous block in digital signal processing applications. Its characteristics are determined by its coefficients, which are the intellectual property (IP) for its designer. However, in a hardware efficient realization, its coefficients become vulnerable to reverse engineering. This paper presents a filter design technique that can protect this IP, taking into account hardware complexity and ensuring that the filter behaves as specified only when a secret key is provided. To do so, coefficients are hidden among decoys, which are selected beyond possible values of coefficients using three alternative methods. As an attack scenario, an adversary at an untrusted foundry is considered. A reverse engineering technique is developed to find the chosen decoy selection method and explore the potential leakage of coefficients through decoys. An oracle-less attack is also used to find the secret key. Experimental results show that the proposed technique can lead to filter designs with competitive hardware complexity and higher resiliency to attacks with respect to previously proposed methods.

关键词： hardware obfuscation IP protection reverse engineering oracle-less attack digital FIR filter design.

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Challenges and opportunities in heterogenous integration during design and process co-optimization. 67

Challenges and opportunities in heterogenous integration dur...

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67th ieee International Midwest symposium on circuits and systems (MWSCAS)

作者： Torres, J. Andres Siemens Digital Ind Wilsonville OR 97070 USA

ISBN: (纸本)9798350387186;9798350387179

In the process of seeking more efficient form factors for electronic devices that meet power, performance and latency requirements, heterogenous integration has risen to become one of the most promising areas to meet the demand of new products that meet very strict cost, performance, latency and power requirements. Whereas traditional board integration of different components meets cost requirements, it does not meet performance and/or latency requirements. In the same manner systems-On-Chip (SOCs) may meet performance and form factor requirements but not cost. By increasing the complexity in which silicon dies are integrated together, it may be possible to deliver unique functionality at lower cost and faster time to market. As the manufacturing complexity increases, design flows must be updated to accommodate a large variety for techniques allowing wiring redistribution, 2.5D interposers, 3D stacking, Plasma dicing, and Through Silicon vias (TSVs). In this work, we focus on the parallels between semiconductor processes and packaging processes, and outline a possible path to enhance heterogeneous packaging operations with techniques developed in semiconductor manufacturing.

关键词： Heterogenous integration Machine Learning Digital Twin Feature Engineering

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Towards Polynomial Formal Verification of Complex Arithmetic circuits 25

Towards Polynomial Formal Verification of Complex Arithmetic...

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Drechsler, Rolf Mahzoon, Alireza Goli, Mehran Univ Bremen Inst Comp Sci Bremen Germany DFKI GmbH Cyber Phys Syst Bremen Germany

ISBN: (纸本)9781665494311

With the growing demands for highly area-efficient, delay-optimized, and low-power designs, the complexity of digital circuits is increasing as well. Especially, a wide variety of arithmetic circuits, including different types of adders, multipliers, and dividers have been proposed to meet the demands in applications such as cryptography and Artificial Intelligence (AI). Some of these arithmetic circuits have highly parallel architectures and contain millions of gates;as a result, they are extremely errorprone. In the last 30 years, several formal verification methods have been proposed to verify arithmetic circuits. These methods report very good results when it comes to the verification of adders and structurally simple multipliers. Moreover, their space and time complexities are polynomial, i.e, they are scalable. However, when it comes to the verification of structurally complex multipliers, the story is different. In this paper, we investigate the space and time complexity of verifying a structurally complex multiplier using a word-level verification method. We prove that the space and time complexity is always exponential. Then, we introduce a new verification strategy that takes advantage of several verification engines. We show that the polynomial formal verification of the complex multiplier becomes possible if the correctness of each stage is verified using the proper verification method. Our verification strategy can be applied to other complex digital circuits.

关键词： Logic gates Complexity theory Parallel architectures Time complexity Artificial intelligence Adders Digital circuits

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