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Spatial/temporal decimation on 3DPAC for very low bit rate video transmission

Spatial/temporal decimation on 3DPAC for very low bit rate v...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Chia-Huang Lin Kuei-Ann Wen Institute of Electronic Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)0780354826

In this paper, we use Spatial/Temporal decimation on 3DPAC for very-low-bit-rate video transmission. After combing the decimation in space and time domain, it is also proved that 3DPAC is effective and suitable in very low bit rate application in the environment with limited bandwidth. Wiener interpolator and linear interpolator are applied for quality enhancement. The visual quality can be retained under low bit rate. With the aid of codebook design to gain more compression, 3DPAC would be support the applications with bit rate lower than 40 kbits/s in CIF format and 10 kbits/s in QCIF format.

关键词： Bit rate Interpolation Codecs Bandwidth Vectors Polynomials Wiener filter Video sequences Books Videoconference

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Probabilistic bottom-up RTL power estimation

Probabilistic bottom-up RTL power estimation

引用

ieee International symposium on Quality electronic design

作者： R. Ferreira A.-M. Trullemans J. Costa J. Monteiro DICE Universite Catholique de Louvain Louvain-la-Neuve Belgium INESC Instituto Superior Technico Lisboa Portugal

We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation, which is described by a symbolic local polynomial. We use an efficient gate-level modeling based on the polynomial simulation method and ZBDDs. We present a set of experimental results that show a large improvement in performance and robustness when compared to previous approaches.

关键词： Integrated circuit interconnections Circuit simulation Energy consumption Power dissipation Libraries electronic switching systems design optimization Very large scale integration Arithmetic Logic circuits

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On the hardware design for DES cipher in tamper resistant devices against differential fault analysis

On the hardware design for DES cipher in tamper resistant de...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Lih-Yang Wang Chi-Sung Laih Hang-Geng Tsai Nern-Min Huang Department of Electronic Engineering Southern Taiwan University of Technology Taiwan Department of Electrical Engineering National Cheng Kung University Taiwan

ISBN: (纸本)0780354826

In the past 20 years, DES has been the most widely used symmetric block cipher for information security. Recently, a novel method called Differential Fault Analysis (DFA) has been proposed to attack DES. Under the assumption that the attacker can induce errors into the cipher device, the key of DES can be unveiled easily. The assumed technique is not mature today, but is like to appear in the near future, especially for attacking a tamper resistant device with an embedded DES VLSI chip. In this paper, we proposed a new hardware design for the DES cipher to resist DFA. By adding some protection circuitry, all the unidirectional faults induced into the registers of a DES chip can be detected, and then alter to the cryptosystem immediately. A hardware emulation experiment using Altera's CPLD chip shows the effectiveness of the protection design.

关键词： Hardware Circuit faults Doped fiber amplifiers Protection Information security Very large scale integration Resists Registers Electrical fault detection Fault detection

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LEMINGS: LSI's EMI-noise analysis with gate level simulator

LEMINGS: LSI's EMI-noise analysis with gate level simulator

引用

ieee International symposium on Quality electronic design

作者： K. Shimazaki H. Tsujikawa S. Kojima S. Hirano Development Group4 Advanced LSI Technology Development Center Corporate Semiconductor Development Division Matsushita Elecrric Indusrrial Company Limited Kyoto Japan

EMI (electromagnetic interference) noise has become a more significant problem in high-speed electronic systems. To analyze EMI problems, LSIs should be analysed carefully as the source of EMI noise. However, as the circuit size of the LSIs becomes larger, it becomes more difficult to analyze the noise of these circuits by using a transistor-level simulator. Thus designers need a simulator that covers full-chip size for noise analysis. In this paper, we propose a new EMI noise simulation methodology that uses a gate-level representation for the first time. The noise from the logic gates is simply modeled by a FFT process based on the superimposed triangular current waveform. Because of the compactness of the model, we can reduce the computation dramatically and accomplish a large simulation. Furthermore, we developed a prototype simulator 'LEMINGS' to demonstrate the proposed method for conventional ASIC design flows. The experimental results show that our new EMI analysis method has achieved an outstanding performance, a high capacity to simulate the whole design and a high accuracy that is equivalent to the transistor-level simulator. Information obtained from LEMINGS can also help designers to improve the LSI and electronic systems' design quality.

关键词： Analytical models Electromagnetic interference Circuit noise Circuit simulation Computational modeling High-speed electronics Logic gates Virtual prototyping Application specific integrated circuits Performance analysis

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Evolvable hardware: from on-chip circuit synthesis to evolvable space systems

Evolvable hardware: from on-chip circuit synthesis to evolva...

引用

International symposium on Multiple-Valued Logic

作者： A. Stoica Jet Propulsion Laboratory California Institute of Technology Pasadena CA USA

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments on selected applications, and presents a perspective on the development of the field. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. These characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life. Expanding reconfiguration to other types of spacecraft hardcore (i.e. optics, MEMS, etc.) could lead to evolvable space systems.

关键词： Hardware Circuit synthesis Space vehicles Genetics Circuit simulation electronic circuits Guidelines Fuzzy logic Fault tolerance Circuit faults

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Picoseconds measurement of internal waveforms in integrated circuits using sampling force probing. II. Applications, capabilities, and limitations

Picoseconds measurement of internal waveforms in integrated ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： R.A. Said Electrical Engineering Department United Arab Emirates University Al-Ain UAE

As integrated circuit density and speed increase their testing becomes crucial to the design cycle as well as a difficult task. To provide proper circuit diagnostics, an adequate test instrument must be capable of providing noncontact measurement at internal points in integrated circuits with high spatial and temporal resolution. Techniques based on noncontact pulse sampling electrostatic force microscopy are proving to be successful candidates for the internal testing of high frequency integrated circuits. In these techniques, internal circuit voltages are determined by sensing the local electrostatic force on a miniature probe that is closely positioned above the circuit test point. Recently, a pulse sampling technique that utilizes a pulse width modulation method has been proposed to enhance the temporal resolution of the force microscope instrument. Only a proof of concept of the pulse width modulation method has been presented. This paper demonstrates the capabilities of the method to measure high frequency signals and provides an analysis in terms of its sensitivity and time resolution. Measurement of a 500 Mbit/s clock signal is presented with a temporal resolution of 50 ps. The technique can provide measurements with voltage sensitivity down to 10 mV/sub rms///spl radic/Hz.

关键词： Circuit testing Pulse width modulation Integrated circuit testing Space vector pulse width modulation Signal resolution Integrated circuit measurements Instruments Sampling methods Electrostatics Microscopy

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A low-offset class-AB CMOS operational amplifier

A low-offset class-AB CMOS operational amplifier

引用

ieee International symposium on circuits and systems (ISCAS)

作者： P.K. Chan L. Siek H.C. Tay J.H. Su School of Electrical and Electronic Engineering Nanyang Technological University Singapore

This paper presents a novel systematic offset minimization circuit for designing a class-AB CMOS operational amplifier. The proposed structure has a replica-gain circuit, generating a DC replica bias to the differential input stage, and providing differential gain as well as level conversion to drive the class-AB output stage. Statistical measurements on 15 samples of the amplifier showed the mean and standard deviation of the input offset were of 0.88 mV and 0.49 mV respectively. These results were achieved using an active area of only 3700 /spl mu/m/sup 2/ for the critical differential input stage in a 0.8 /spl mu/m standard CMOS technology.

关键词： Operational amplifiers Differential amplifiers CMOS technology Mirrors Minimization Temperature sensors Current density Circuit noise Character generation design engineering

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An interconnect-driven design of a DFT processor

An interconnect-driven design of a DFT processor

引用

ieee International symposium on circuits and systems (ISCAS)

作者： D. Eckerbert H. Eriksson P. Larsson-Edefors A. Edman Electronic Devices Department of Physics Linköping Universitet Linkoping Sweden Switchcore AB Lund Sweden

A new interconnect-driven DFT implementation is proposed in this paper. The normal way to implement the DFT is to use the FFT algorithm since it is computationally favorable. However, the increased speed comes at the cost of increased communications which give a higher power consumption. If the DFT algorithm is directly implemented instead, each channel becomes independent of all other channels and consequently communications and hence power consumption are reduced. Other benefits of using the DFT directly are the possibility to calculate a spectrum of any length, not only a power of two, and to have an irregular frequency step between channels. A number of ad hoc processing-element (PE) and system-level solutions are also proposed to reduce the power consumption even further.

关键词： Discrete Fourier transforms Energy consumption Frequency Fast Fourier transforms Physics Costs Mobile handsets Computational complexity Jamming Flow graphs

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Low power design of a multi-mode transceiver

Low power design of a multi-mode transceiver

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ieee International symposium on circuits and systems (ISCAS)

作者： D. Soudris M. Perakis X. Mizas V. Mardiris K. Katis C. Dre A.E. Tzimas E.G. Metaxakis G. Kalivas N. Zervas S. Theoharis G. Theodoridis A. Thanailakis C. Goutis VLSI Design and Testing Center Department of Elec & Computer Engineering Democritus University of Thrace Xanthi Greece Department of Computer Engineering and Informatics University of Patras Greece INTRACOM S.A. Paiania Greece Applied Electronics Lab Department of Elec & Computer Engineering University of Patras Greece VLSI Design Lab Department of Elec & Computer Engineering University of Patras Greece

Recent advances in electronic technology integration coupled with increasing needs for more services in portable communications favors the development of high performance dual-mode terminals. We present the complete architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters design. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor and A/D & D/A converters is also described in detail manner. The whole architecture of the modulator/demodulator was described by VHDL hardware language, synthesised and implemented in Xilinx environment.

关键词： Transceivers Digital modulation Demodulation Finite impulse response filter GSM Very large scale integration Signal processing Digital-analog conversion Clocks Testing

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Passive reduced-order modeling via Krylov-subspace methods

Passive reduced-order modeling via Krylov-subspace methods

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ieee International symposium on Computer Aided Control System design (CACSD)

作者： R.W. Freund Bell Laboratories Murray Hill NJ USA

ISBN: (纸本)0780365666

Krylov-subspace methods have become popular tools for reduced-order modeling of large-scale time-invariant linear dynamical systems. These techniques produce in a Pade sense optimal reduced-order models. However, when applied to passive systems, the Pade models do not preserve passivity in general. We describe a Krylov-subspace technique that generates passive reduced-order models. Results of numerical experiments with a passive system arising in VLSI circuit simulation are reported.

关键词： Reduced order systems Circuit simulation Large-scale systems Very large scale integration RLC circuits Transfer functions Surges electronic circuits Differential algebraic equations Nonlinear equations

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