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Improved current-feedback op-amp with good DC and CMRR performance

Improved current-feedback op-amp with good DC and CMRR perfo...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： K. Hayatleh W.J. Su F.J. Lidgey Department of Electronic Engineering School of Engineering Headington Oxfordshire UK Qualcomm Inc. San Diego CA USA

A novel high DC accuracy and high CMRR performance current-feedback op amp (CFOA) is presented. The conventional architecture CFOA suffers from poor DC gain accuracy and CMRR due mainly to Early effects in the input stages. The new design is based on a bootstrapping technique applied to the input stage, and results in a CFOA with DC performance, CMRR and gain accuracy all substantially improved. All of these improvements are obtained without increase in circuit complexity and power consumption. Most of the other characteristics of the new CFOA are similar to those of a conventional design.

关键词： Operational amplifiers Voltage Energy consumption Degradation Performance gain Circuit noise Circuit simulation Complexity theory Bandwidth Power amplifiers

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A wide-range tunable bandpass filter cum sinusoidal oscillator using a new current-controlled resistor

A wide-range tunable bandpass filter cum sinusoidal oscillat...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： S. Kumar A. Govil A. Bhattacharyya D. Dutta Epic Systems Corporation Madison WI USA River Run Group Madison WI USA Delhi College of Engineering Madison WI USA Department of Electronic Computer Engineering Madison WI USA

The proposed design uses the exponential characteristic of BJTs to produce a new current-controlled resistor that can be electronically varied from 10 /spl Omega/ to several M/spl Omega/. This resistor is used to make a bandpass filter, the resonant frequency of which is linearly tunable to a wide range of 10 Hz to 35 MHz. The filter achieves a constant Q-factor of about 30 at all frequencies (when implemented with discrete devices). The same configuration also realizes a linearly tunable sinusoidal oscillator for all frequencies. The versatility and usefulness of this low-cost design is shown by simulating a swept-tuned spectrum analyzer and a tracking (Bode plot) generator. The circuit uses only nine small-valued passive components.

关键词： Band pass filters Oscillators Resists Resistors Diodes Tunable circuits and devices Frequency Voltage Circuit simulation Manufacturing

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Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation

Implementation of maximally fast ladder wave digital filters...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： O. Gustafsson L. Wanhammar Department of Electrical Engineering Linkoping University Linkoping Sweden

Ladder wave digital filters is a class of IIR digital filters derived from double resistively terminated ladder networks, which gives them good stability and low sensitivity to variations in the element values. An approach to design maximally fast bit-serial ladder wave digital filters is presented based on the numerically equivalent state-space representation of the signal-flow graph. An algorithm for finding the minimal sample period from the numerically equivalent state-space representation is also given. Maximally fast filters is an efficient way to achieve low power consumption on the algorithmic level. Further, we show an approach to map the operations to an optimal hardware structure, that can be implemented using bit-parallel, digit-serial, or bit-serial arithmetic.

关键词： Digital filters Frequency Delay effects Stability IIR filters Power supplies Voltage Reactive power electronic mail Signal design

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design and analysis of digital audio amplifier using ZVS PWM converter

Design and analysis of digital audio amplifier using ZVS PWM...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： W.H. Lau H.S.H. Chung C.M. Wu N.K. Poon Department of Electronic Engineering City University Hong Kong China

This paper presents a simple methodology to convert a hard-switched pulse-width-modulated (PWM) H-bridge converter used in classical digital audio amplifiers into a zero-voltage-switching (ZVS) converter. ZVS is simply achieved by connecting an L-C series branch across the converter output. ZVS occurs during the dead time interval of the PWM signals, giving an effective improvement in the conversion efficiency, output frequency spectrum, and total harmonic distortion (THD). Simplified design procedures are given for choosing the value of the components. A prototype having output power of 20 W and with switching frequency of 705.6 kHz has been built and the experimental results are presented.

关键词： Pulse width modulation Zero voltage switching Pulse amplifiers Pulse width modulation converters Joining processes Frequency conversion Total harmonic distortion Prototypes Power generation Switching frequency

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A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications

A dual 3-V 32-MS/s CMOS switched-current ADC for telecommuni...

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ieee International symposium on circuits and systems (ISCAS)

作者： B.E. Jonsson H. Tenhunen Microelectronics Ericsson Radio Systems AB Stockholm Sweden Electronic System Design Laboratory ETH-Electrum Royal Institute of Technology Stockholm Sweden

The potential for switched-current A/D converters in low-voltage, telecommunication applications with a high level of integration is investigated through a test design. A dual, 3 V, 32 MS/s A/D converter was fabricated in a standard digital 5 V, 0.8 /spl mu/m CMOS process. Fully differential first-generation switched-current circuits with common-mode feedforward are used to implement a 1.5-b/stage pipelined ADC core. Eight time-interleaved ADC cores operating at 4 MS/s are used to achieve a high sample rate. With channel compensation, the measured SFDR is more than 50 dB at 32 MS/s with f/sub in/=1.13 MHz. The ADC-core was measured to have 60.3 dB peak SFDR, 46.5 dB peak SNDR, and approximately 20 MHz input bandwidth. The resolution of the parallel ADC was limited by additional noise and the useful bandwidth was lowered by a fixed-pattern timing error that could not be removed by channel calibration.

关键词： Telecommunication switching Calibration CMOS technology Frequency estimation circuits Timing Wideband Mirrors CMOS process Bandwidth

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Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis

Reduced complexity, high performance digital delta-sigma mod...

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ieee International symposium on circuits and systems (ISCAS)

作者： L. Sun T. Lepley F. Nozahic A. Bellissant T. Kwasniewski B. Heim Department of Electronic Carleton University Ottawa ONT Canada

This paper presents the design consideration of high order digital /spl Delta//spl Sigma/ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (MASH 1-2) is designed and implemented which allows for the input to operate over 75% of the input adder capacity. The number of the output levels is reduced to two bits. The circuit was verified through simulation, ASIC implementation and exhibits high potential for a gigahertz range, low-power monolithic CMOS frequency synthesizer.

关键词： Delta-sigma modulation Frequency synthesizers Multi-stage noise shaping Noise shaping Phase noise Filters Phase locked loops Bandwidth Delta modulation circuits

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Combinatorial architectural level power optimization for a class of orthogonal transforms

Combinatorial architectural level power optimization for a c...

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ieee International symposium on circuits and systems (ISCAS)

作者： I.B. Dhaou H. Tenhunen R. Inst. of Technol. Kista Sweden Electronic System Design Laboratory Department Of Electronics KTH-Electrum Electrum-229 Royal Institute of Technology Kista Sweden

In this paper, we present a new technique for low-power architecture synthesis of a class of orthogonal transforms. The core of this technique is based on combinatorial optimization, where the metrics of the graph are computed using architectural level power dissipation (ALPD). The ALPD uses the electrical characteristics of the basic building blocks or intellectual property (IP). Thus, it requires a well-characterized low-power library. The advantage of this technique is the optimal architecture selection at high-level of the design abstraction. We demonstrate this technique for low-power architecture synthesis implementing N-point fast Fourier transform (FFT) and fast wavelet transform (FWT). Moreover we developed a model for low-power library characterization of the arithmetic units, using a linear regression, having an accuracy over 80% when comparing with Spice level simulation.

关键词： Signal processing algorithms Discrete transforms circuits Arithmetic US Department of Transportation Discrete wavelet transforms Power dissipation Libraries Fast Fourier transforms Linear regression

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design and analysis of an ultra low-voltage CMOS class-AB V-I converter for dynamic range enhancement

Design and analysis of an ultra low-voltage CMOS class-AB V-...

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ieee International symposium on circuits and systems (ISCAS)

作者： C.-H. Lin M. Ismail Analog VLSI Laboratory Department of Electrical Engineering Ohio State Uinversity USA

This paper presents the design technique and comprehensive analysis of an ultra low voltage V-I converter. Under the requirement of high frequency and low voltage applications, internal linear small signal processing is applied to achieve the ultra low voltage operation with large input signal swing. A local feedback loop is introduced to optimize the design. In a 1.2 /spl mu/m n-well CMOS experimental result, the proposed CMOS V-I converter has a /spl plusmn/0.25 V highly linear differential-input swing with 1.2 V supply voltage and achieves an almost rail-to-rail differential-input swing with at least 1.5 V supply-voltage. This V-I converter has 1.2% THD of fully-rail swing (/spl plusmn/1.5 V) with low power consumption. Dynamic input range is 80 dB with 1% THD output signal.

关键词： Dynamic range Threshold voltage Low voltage Signal processing Feedback loop circuits Very large scale integration Distortion Signal resolution electronic mail

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2-V 900-MHz quadrature coupled LC oscillators with improved amplitude and phase matchings

2-V 900-MHz quadrature coupled LC oscillators with improved ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Chi-Wa Lo H.C. Luong Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Kowloon Hong Kong China

Coupled LC oscillators are known to provide good performance in terms of phase noise, signal amplitude, power consumption, and quadrature output signals. However, IQ amplitude and phase mismatches in these oscillators can be quite large due to the serious mismatch problem of large area inductors and varactors. A simple design modification of the coupled LC oscillators shows a significant improvement of the amplitude and phase mismatches. Detailed operational principle is examined. A 2 V 900 MHz prototype using this simple idea has been designed.

关键词： Frequency conversion Phase noise Inductors Varactors CMOS technology Voltage-controlled oscillators Couplings Power engineering and energy Energy consumption Prototypes

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A lower bound on general minimal resource interval scheduling with arbitrary component selection

A lower bound on general minimal resource interval schedulin...

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ieee International symposium on circuits and systems (ISCAS)

作者： Z.X. Shen C.C. Jong Institute of High Performance Computing National University Singapore School of Electrical and Electronic Engineering Nanyang Technological University Singapore

Exploring lower bound of scheduling is an important problem in high-level synthesis, In this paper, we address the problem of computing lower bound on the general minimal resource interval scheduling problem, called n-n-MRIS, in which arbitrary component selections are allowed in stead of the traditional unicomponent selection. The problem of n-n-MRIS is proved to be strongly NP hard. An efficient ILP model and a surrogate relaxation technique are proposed to produce a lower bound for the n-n-MRIS problem.

关键词： Processor scheduling Magnetic resonance imaging High level synthesis Costs High performance computing Algorithm design and analysis Space exploration Hardware Performance loss Integer linear programming

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