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ieee International symposium on circuits and systems (ISCAS)

作者： M. Fedeli C. Vacchi Electronic Department University of Pavia Italy

A self-biased CMOS transconductor stage, able to work with a low-voltage supply and low-power dissipation, is proposed. A fully differential configuration in a 0.25 /spl mu/m minimum lithography technology has been utilized to design the circuit. Paying particular attention to the mismatch problems, a correct sizing of the circuit has been made. With a voltage supply of 1.2 V, the power consumption is 200 /spl mu/W and the gain bandwidth product is equal to 30 MHz. Utilizing the transconductor proposed here, a biquadratic cell has been simulated: imposing a central frequency of 1 MHz, the filter reaches 1% of THD with 275 mV peak differential sinusoidal input signal, while the total input noise is about 190 /spl mu/V/sub r.m.s./. With a power consumption of 1 mW, the cell presents a dynamic range of 60 dB and a SNDR peak of 48.6 dB.

关键词： Low voltage Transconductors Energy consumption Lithography CMOS technology Bandwidth Circuit simulation Frequency Filters Dynamic range

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Monolithic GaAs-InGaP HBT balanced vector modulators for millimeter-wave wireless systems

Monolithic GaAs-InGaP HBT balanced vector modulators for mil...

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ieee symposium on Radio Frequency Integrated circuits (RFIC)

作者： A.E. Ashtiani T. Gokdemir A. Vilches Z. Hu I.D. Robertson S.P. Marsh Department of Electronic Engineering King''s College University of London UK Microwave and Systems Research Group University of Surrey Guildford UK Marconi Caswell Limited Towcester UK

This paper describes the design and performance of millimeter-wave balanced vector modulators employing the Marconi HBT MMIC technology. Two versions have been fabricated for operation at 38 GHz; the first employs normal Lange couplers whilst the second employs miniaturised microstrip couplers, which reduce the MMIC chip area by more than 40%. With a simple bias calibration technique the circuits achieve near-perfect constellations with negligible amplitude and phase errors over a wide bandwidth.

关键词： Gallium arsenide Heterojunction bipolar transistors Amplitude modulation Phase modulation Couplers MMICs FETs Switches Millimeter wave technology Millimeter wave radar

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design of GaAs MMIC transistors for the low-power low noise applications

Design of GaAs MMIC transistors for the low-power low noise ...

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ieee symposium on Radio Frequency Integrated circuits (RFIC)

作者： Z.M. Nosal Institute of Electronic Systems Warsaw University of Technology Warsaw Poland

The paper investigates the problem of minimizing bias power for the low noise GaAs amplifiers. The model of the amplifier parameters versus transistor gate width is presented and used to derive the conditions for noise optimization. It is shown that optimum FETs are rather wide and may operate at very low current densities. Complete amplifier stages with only 3-5 mW bias power are feasible at 2 GHz with noise figures below 1 dB.

关键词： Gallium arsenide MMICs Noise figure Low-frequency noise Low-noise amplifiers Microwave transistors Circuit noise Noise measurement Microwave FETs Impedance

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Q-enhancing technique for rf CMOS active inductor

Q-enhancing technique for rf CMOS active inductor

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ieee International symposium on circuits and systems (ISCAS)

作者： U. Yodprasit J. Ngarmnil Department of Electronic Engineering Faculty of Engineering Mahanakom University of Technology Bangkok Thailand

A design technique for realising a very-high Q CMOS active inductor operating in the RF-band is described in this paper. The proposed active inductor is based on double-feedback transconductor topology in which negative feedback is used to realise inductive input impedance while positive feedback is employed to produce a negative resistance for canceling the inductor loss, hence an enhancing of the Q factor. In order to verify the effectiveness of the proposed technique, a very-high Q (Q>1,000) second-order bandpass filter has been implemented. Simulation results show that the filter exhibits stable Q factor of 12,000, the resonant frequency can be tuned from 1.007 GHz to 1.023 GHz and the input-referred third-order intercept point (IIP3) of -25 dBm (at 1.023 GHz centre frequency and 12,000 Q factor) under a 3.3 V supply voltage.

关键词： CMOS technology Active inductors Q factor Negative feedback Band pass filters Transconductors Topology Impedance Resonant frequency Voltage

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A 2-V 900-MHz CMOS mixer for GSM receivers

A 2-V 900-MHz CMOS mixer for GSM receivers

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ieee International symposium on circuits and systems (ISCAS)

作者： Toby Kwok-Kei Kan Kin-Chung Mak Dongsheng Ma H.C. Luong Department of Electrical & Electronic Engineering Hong Kong University of Science and Technology Hong Kong China

A 2-V 900-MHz downconversion mixer to be used in a single-chip CMOS receiver is presented. The mixer is based on a Gilbert cell but uses two source-followers as current modulators rather than a common-source input stage in order to support low-voltage operation and to improve the linearity. Two prototypes have been made for different design trade-off. The first mixer prototype achieves a measured conversion gain of -8 dB and an IIP3 of 26 dBm with a power consumption of 1.5 mW from a 3-V supply. The second prototype has a measured conversion gain of -2 dB, a noise figure (NF) of 22 dB and an IIP3 of 6 dBm with a power consumption of 3 mW from a single 2-V supply.

关键词： GSM Mixers Linearity Prototypes Radio frequency CMOS technology Frequency conversion RF signals Voltage Power measurement

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design and analysis of transient-suppression-devices based on SPICE-simulation

Design and analysis of transient-suppression-devices based o...

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ieee International symposium on Electromagnetic Compatibility (EMC)

作者： T. Weber J.L. ter Haseborg Department of Measurement Engineering and Electromagnetic Compatibility University of Technology Hamburg-Harburg Hamburg Germany

In order to meet the requirements of EMC directives and to obtain a high reliability of electronic systems, nonlinear protection circuits are necessary to suppress overvoltages and fast transients. Especially for RF-applications the designer has to match contrary criteria concerning the suppression of the transients and the influence on the transmitted information signal due to attenuation, reflection and nonlinear distortions. Therefore a systematic design approach for nonlinear protection circuits based on SPICE has been developed, which makes it possible to perform simulations both in the time- and frequency-domain and to determine the energy transferred to the load, that has to be protected. Furthermore evolutionary algorithms have been used to compute models for the precise simulation of the RF-characteristics (S-parameters) of the nonlinear protection circuit.

关键词： Transient analysis Computational modeling Circuit simulation Electromagnetic compatibility Surge protection Signal design Attenuation Reflection Nonlinear distortion SPICE

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A high-frequency high-Q CMOS active inductor with DC bias control

A high-frequency high-Q CMOS active inductor with DC bias co...

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Midwest symposium on circuits and systems (MWSCAS)

作者： A. Ilker Karsilayan R. Schaumann Department of Electrical Engineering Texas A and M University College Station TX USA Department of Electrical and Computer Engineering Portland State University Portland OR USA

The design of a very simple CMOS high-Q active inductor suitable for applications at low supply voltage and high frequencies is discussed. The inductor value, L, and the quality factor, Q, are independently adjustable by two PMOS varactors (variable capacitors). Alternatively, L can be tuned via a bias current. The inductor's DC level is set by a bias voltage. The self-resonance frequency, f/sub r/, is larger than 1GHz and very high values of Q, up to Q=/spl infin/, can be obtained so that circuit can be used for constructing high-frequency oscillators. The performance of the electronic inductor is demonstrated by simulation.

关键词： Active inductors Frequency Q factor Circuit stability Voltage Equivalent circuits Circuit simulation Circuit noise CMOS technology Admittance

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Correct-by-design CAD enhancement for EMI and signal integrity

Correct-by-design CAD enhancement for EMI and signal integri...

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ieee International symposium on Quality electronic design

作者： E.A. McShane K. Shenai Microsystems Research Center Department of Electrical Engineering and Computer Science University of Illinois Chicago USA

The monolithic integration of mixed-signal and RF microelectronics is straining the capabilities of present CAD roots for predictive analysis. In particular, the effects of di/dt, crosstalk, high-frequency impedance matching, and substrate noise pose challenges to reliable circuit operation. This is especially true as supply rail voltages continue to shrink below 2.5 V. Although PCB CAD tools have successfully addressed these issues, similar. tools have yet to penetrate the VLSIC/RFIC market due to the even greater signal frequencies and far greater network density. We describe an ongoing research effort to introduce models of these effects into a commercial CAD tool. The goal is to develop a correct-by-design CAD system in which constraints on signal crosstalk and EMI are considered along with signal delay and power restrictions in performing automated floor-planning and routing. To permit top-down synthesis of reliable systems, we are also expanding the HDL coding of digital systems to include two additional parameters: EMI victim status and EMl point-source contributions.

关键词： Electromagnetic interference Crosstalk Monolithic integrated circuits Radio frequency Microelectronics Impedance matching Circuit noise Integrated circuit reliability Rails Voltage

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A modified two-step SOVA-based turbo decoder with a fixed scaling factor

A modified two-step SOVA-based turbo decoder with a fixed sc...

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ieee International symposium on circuits and systems (ISCAS)

作者： Dai Won Kim Taek Won Kwon Jun Rim Choi Jun Jin Kong School of Electrical Engineering Kyungpook National University Taegu South Korea Communication Network Systems Samsung Electronics Central Research Laboratory

ISBN: (纸本)0780354826

In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 /spl mu/m Samsung SOG technology using Verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.

关键词： Decoding Viterbi algorithm Concatenated codes Convolutional codes Delay lines electronic mail Communication networks Telecommunication network reliability Hardware design languages Bit error rate

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An efficient algorithm for digital circuits testing

Advances in Physics, Electronics and Signal Processing Appli...

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Advances in Physics, electronics and Signal Processing Applications 2000年 133-137页

作者： Dugonik, Bogdan Lab. for Microelectronic Systems Fac. of Elec. Eng. and Comp. Science Smetanova 17 2000 Maribor Slovenia

ISBN: (纸本)9608052173

With complex integrated circuits implemented either in FPGAor densely packed printed boards the testability problem arises. Since its inception in the mid eighties and its adoption by the ieee organization as an international standard, boundary-scan technology has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. This paper presents an efficient sequential circuit automatic test generation algorithm in conjunction with boundary scan technology. Software tools include Automatic boundary-scan Test Program Generator (ATPG) and boundary-scan diagnostics. Most pattern generators employ D-algorithm, Podem, Lasar or other known methods. The algorithm is based on circuit simulation which has implemented a primitive error model to obtain a list of responses for each implemented failure. Test stimuli for automatic test equipment can be obtained either from test vectors written by circuit designers and/or diagnostics engineers, from an automatic test pattern generator (ATPG) or from some combination of these sources. The test response can be obtained either by simulating the test stimuli or by running the test stimuli on a reference board and monitoring response. We have studied an alternative method for creating an optimal test for testing digital combinational or sequential circuits on single "stuck at" failures. The final result is a diagnostic and statistical file that enables us to obtain optimal test vectors for maximal fault coverage or for distinguishing the detected faults in order to obtain better fault diagnostics. We designed a fault-detection experiment in an implemented FPGA design supported by boundary scan emulator.

关键词： Digital circuits

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