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design of fault-tolerant solid state mass memory

Design of fault-tolerant solid state mass memory

引用

ieee International symposium on Defect and Fault Tolerance in VLSI systems

作者： G.C. Cardarilli P. Marinucci S. Bertazzoni M. Salmeri A. Salsano Department of Electronic Engineering University of Roma Tor Vergata Italy Consortium ULISSE Italy

ISBN: (纸本)076950325X

This paper presents the flow used for the design of a fault-tolerant solid state mass memory (SSMM) based on commercial off the shelf (COTS) 64 Mb DRAMs. The effects of high-energy radiations on these devices are often complex. In particular, in the paper we consider heavy ion and proton induced soft and hard errors in DRAM devices. In our work, these errors are mitigated at system level rather at device level. In fact the mass memory is based on a suitable ECC code that improves its tolerance with respect to errors induced in DRAMs. The definition of a SSMM architecture is very complex since the design has to take into account the radiation environment and the different system constraints. In this paper we presents the methodology, derived from the operational research theory, used to select the codes and the memory architecture, taking into account the different design constraints.

关键词： Fault tolerance Solid state circuits Error correction codes Read-write memory Satellite ground stations Error correction Read only memory Robustness Stress Energy consumption

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High-speed, low-power digital and analog circuits implemented in IBM SiGe BiCMOS technology

High-speed, low-power digital and analog circuits implemente...

引用

Annual ieee symposium on Gallium Arsenide Integrated Circuit (GaAs IC)

作者： K.E. Fritz B.A. Randall G.J. Fokken W.L. Walters M.J. Lorsung A.D. Nielsen J.F. Prairie D.J. Post D.R. Greenberg B.K. Gilbert Special Purpose Processor Development Group Mayo Foundation Rochester MN USA IBM East Fishkill Facility Hopewell Junction NY USA

Under the auspices of Defense Advanced Research Project Agency Microsystems Technology Office (DARPA/MTO) Low Power electronics Program, the Mayo Foundation is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being explored by Mayo include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation by Mayo to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS technology are presented.

关键词： Analog circuits Silicon germanium Germanium silicon alloys Integrated circuit technology BiCMOS integrated circuits Circuit testing Low power electronics Energy consumption Radar applications Radar signal processing

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An overview of the NCMS/StorageTek embedded decoupling capacitance project

An overview of the NCMS/StorageTek embedded decoupling capac...

引用

International symposium on Advanced Packaging Materials

作者： P.H. Bowles R. Charbonneau Delphi Delco Electronic Systems USA Storage Technology Corporation UK

The need for power-ground decoupling capacitance is nearly universal in electronic circuits. NCMS, NEMI and StorageTek have organized a project aimed at advancing the use of embedded capacitance technology for power supply decoupling. Embedding the capacitance in the PWB frees up space that can be used for other functions. The technology may also improve performance and reliability by reducing the number of solder joints and discrete capacitors, and the associated failure modes. Total system cost may also be lowered as a result of parts reduction and circuit integration. This presentation reviews the details of the project including project members, goals and objectives, test vehicle design, material considerations, electrical and qualification testing, modeling, deliverables, and timeline. This is a short-term project, intended to evaluate available materials, and to result in usable (designable, manufacturable, and cost-effective) embedded capacitance. The ultimate aim is to make this new technology a practical alternative in the very near future.

关键词： Capacitance Space technology Circuit testing Materials testing electronic circuits Power supplies Integrated circuit reliability Power system reliability Soldering Capacitors

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Modeling and automating selection of guarding techniques for datapath elements 99

Modeling and automating selection of guarding techniques for...

引用

International symposium on Low Power electronics and design (ISLPED)

作者： W.E. Dougherty D.E. Thomas Center for Electronic Design Automation Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

ISBN: (纸本)9781581131338

While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal savings. Three new internal guarding techniques are presented in adders that increase energy savings up to 38% over existing external guarding techniques. This allows guarded evaluation to be effective at duty cycles as much as 20% higher than are currently practical. A modeling methodology is presented defining the energy and energy delay of a unit in a generic application space. These models can easily be incorporated into an automated selection technique to determine the optimal guarded implementation. This technique is tested on a DSP ASIP, increasing overall energy savings by preventing unnecessary guarding. The data is generalized and it is observed that guarding is most beneficial when the ratio of guarding transistors to driven computational transistors is 1/10 or lower.

关键词： Logic Latches Digital signal processing Application specific processors Circuit synthesis Libraries electronic design automation and methodology Digital arithmetic Adders Delay

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Application of the finite difference time domain (FDTD) method to a challenging real-world EMC problem

Application of the finite difference time domain (FDTD) meth...

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ieee International symposium on Electromagnetic Compatibility (EMC)

作者： I. Rumsey M. Piket-May Department of Electrical and Computer Engineering University of Colorado Boulder CO USA

As high speed systems place greater demands on electronic packaging and interconnects, numerical simulation at the package and circuit board levels before prototyping is needed to produce designs which meet stringent EMI, EMC, signal integrity, and timing constraints. The finite-difference time-domain technique is an intuitive modeling technique that may be used for a number of interesting EMC problems. This paper discusses initial results for grand challenge problems 2 and 4.

关键词： Finite difference methods Time domain analysis electronics packaging Electromagnetic compatibility Integrated circuit interconnections Numerical simulation Printed circuits Virtual prototyping Signal design Electromagnetic interference

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Analysis and design of a resonant battery charger for photovoltaic systems

Analysis and design of a resonant battery charger for photov...

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ieee International symposium on Industrial electronics (ISIE)

作者： R.M. Lamaison J. Bordonau A. Esquivel J. Peracaula Department of Electronic Engineering Universitat Politecnica de Catalunya Barcelona Spain CETYS Tijuana Baja California Mexico

A solar battery charger using a DC/DC resonant converter with 3 reactive elements operating over a wide load range is presented. This charger is based on a half bridge inverter structure and it can be fed by a solar panels system configured as two current sources, An experimental 100 W/250 kHz unit was built and tested in the laboratory. The operation has been verified with a rechargeable lead-acid battery of 12 V and 1.2 Ah and a HP 6030A DC current source of 200 V and 17 A controlled by a personal computer. The current source follows the characteristic curve of the solar panels.

关键词： Resonance Batteries Photovoltaic systems Solar power generation Bridge circuits Power generation Voltage Switching converters Inverters Power supplies

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Reduced latency ieee floating-point standard adder architectures

Reduced latency IEEE floating-point standard adder architect...

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Computer Arithmetic (ARITH)

作者： A. Beaumont-Smith N. Burgess S. Lefrere C.C. Lim CHiPTec Department of Electrical and Electronic Engineering University of Adelaide Adelaide Australia

The design and implementation of a double precision floating-point ieee-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.

关键词： Delay Adders circuits Microprocessors Pipeline processing Arithmetic Hardware electronic switching systems Very large scale integration Digital signal processors

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Monolithic millimeter-wave balanced bi-phase amplitude modulator in GaAs/InGaP HBT technology

Monolithic millimeter-wave balanced bi-phase amplitude modul...

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Microwave, MTT-S International symposium

作者： S. Nam N. Shala K.S. Ang A.E. Ashtiani T. Gokdemir I.D. Robertson S.P. Marsh Department of Electronic and Electrical Engineering Microwave & Systems Research Group University of Surrey Guildford Surrey UK Microwave Circuits and Devices Group King''s College UK Marconi Materials Technology Limited Towcester Northamptonshire UK

The design and performance of a monolithic 38 GHz balanced reflection-type direct carrier modulator in HBT technology is described. The circuit uses cold-HBTs as variable resistance reflection terminations. With a calibrated biasing technique, the circuit achieves /spl plusmn/0.1 dB amplitude error and /spl plusmn/1.5/spl deg/ phase error.

关键词： Millimeter wave technology Amplitude modulation Gallium arsenide Heterojunction bipolar transistors Voltage Attenuators Capacitance measurement Electrical resistance measurement PHEMTs Insertion loss

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Prediction of radiated perturbations from currents inside slotted screens using a hybrid FEM procedure

Prediction of radiated perturbations from currents inside sl...

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Antennas and Propagation Society International symposium

作者： L. Nuno J.V. Balbastre E. de los Reyes Department of Communications Polytechnic University of Valencia Spain

electronic systems use electric currents in its normal work, but these currents will also be the origin of radiated perturbations that could affect the performance of neighbor systems. Thus, these circuits are enclosed in some kind of envelope or shield, in order to reduce the amplitude of the perturbations produced by them. Nevertheless, the external envelopes must sometimes be slotted, in order to connect the covered circuit to the exterior world (the expansion slots in PCs are a very common example). Unfortunately, these slots will radiate some electromagnetic perturbations, but an accurate design can keep them under critic values. As is shown, traditional models based on aperture antennas can fail when some effects (like edge effects) are not negligible, so a numerical approach is needed. The problem of slotted screens has been studied in the past from the point of view of electromagnetic susceptibility (EMS) using different numerical techniques. A number of have authors presented a hybrid procedure based on the finite element method (FEM) and modal analysis that was successfully applied to the study of EMS problems in slotted envelopes. In this work, this procedure has been adapted for solving the electromagnetic interference problem.

关键词： circuits Medical services Current Personal communication networks Electromagnetic radiation Electromagnetic shielding Aperture antennas Finite element methods Modal analysis Electromagnetic interference

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Environmental performance of mobile products

Environmental performance of mobile products

引用

ieee International symposium on electronics and the Environment

作者： B. Ram A. Stevels H. Griese A. Middendorf J. Muller N.F. Nissen H. Reich Environmental Competence Center Philips Consumer Electronics Company Eindhoven Netherlands Delft University of Technnology Delft Netherlands Fraunhofer Institute of Reliability and Microintegration (IZM) Berlin Germany

ISBN: (纸本)0780354966

Digitalization, miniaturization and integration are strong drivers for further development of products for mobile communication. As such these will generally lead to lower environmental loads per product. However, the strongly increasing number of products on the market will reverse this trend for the total sector. Examinations on telephones have been carried out jointly at Philips Consumer electronics and at the Fraunhofer Institute for Reliability and Microintegration (IZM). The characteristic product parts, energy supply, display, encasing and electronic signal processing are subjected to an environmental assessment (including environmental assessment with Eco-Indicator and with the Toxic Potential Indicator IZM-TPI) and improvement potentials are shown for the selected products. The analysis shows that in mobile products, energy systems and the printed circuit boards are the key elements in further reduction of environmental loads. Both alternative substrates, lead free soldering and component selection (less hazardous substances) can contribute substantially towards this goal. These three topics are combined with further miniaturization, especially reduction of the board size, in the future. Approximately only half of the potential in this field has been implemented yet. As an overall result, it is concluded that the environmentally based load of present and future mobile products can be kept within limits if a swift implementation of Ecodesign (design for environment) is ensured.

关键词： Lead Consumer electronics Driver circuits Mobile communication Telephony Displays Signal processing Printed circuits Environmentally friendly manufacturing techniques Soldering

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