This paper presents an analytical approach to the design of CMOS cross-coupled inverter sense amplifiers. The effects of the equilibrating transistors and the tail current source on the speed of the sense amplifier ar...
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ISBN:
(纸本)0780344553
This paper presents an analytical approach to the design of CMOS cross-coupled inverter sense amplifiers. The effects of the equilibrating transistors and the tail current source on the speed of the sense amplifier are analyzed. An analysis of the offset due to mismatch in various parameters is performed, showing that a complete offset analysis has to account for the cell and bitline structure. A new figure of merit for the offset in the sense amplifier and several new design insights are introduced.
Four CMOS RF low noise amplifier (LNA) circuits have been analyzed. These analyses include the effect of induced gate noise for the MOSFET The noise factor contribution from each noise source is derived and these circ...
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ISBN:
(纸本)0780344553
Four CMOS RF low noise amplifier (LNA) circuits have been analyzed. These analyses include the effect of induced gate noise for the MOSFET The noise factor contribution from each noise source is derived and these circuits are then compared for a minimum noise factor: The MOSIS HP 0.35 mu m and 0.8 mu m CMOS technologies have been used for performance comparisons. An automatic synthesis system for LNA design is also described.
Large signal models needed for fast time domain modelling of oscillator circuits are considered. The models are based on harmonic linearization and derived for conventional time domain simulators. The paper describes ...
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ISBN:
(纸本)0780344553
Large signal models needed for fast time domain modelling of oscillator circuits are considered. The models are based on harmonic linearization and derived for conventional time domain simulators. The paper describes the techniques for the use of first harmonic of driving signal only. The model consists of three coupled parts: DC, real, and imaginary subcircuits. Building of those subcircuits for exponential non-linearity is simple and could be recommended as basic for other nonlinearities. Several modelling experiments with oscillator circuits are shortly reviewed.
In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determi...
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ISBN:
(纸本)0780344553
In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency: (i) optimization to a single modulation index point, and (ii) optimization to a range of modulation indices. For the design of an output stage with optimum power efficiency (and small IC area), we recommend the waffle layout realization optimized to a range of modulation indices. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.
A novel current-mode CMOS transimpedance amplifier is described. The design uses a common-gate regulated cascode configuration providing low input impedance and low input current noise. HSPICE simulations using a 0.6 ...
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ISBN:
(纸本)0780344553
A novel current-mode CMOS transimpedance amplifier is described. The design uses a common-gate regulated cascode configuration providing low input impedance and low input current noise. HSPICE simulations using a 0.6 mu m CMOS process give 3.5GHz bandwidth, 61dB transimpedance gain, 4.2 pA/ root Hz equivalent input noise current spectral density, and 135mW power consumption. Measured results of a previous test chip are also presented.
This paper presents a design methodology for MOS amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an eva...
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This paper presents a design methodology for MOS amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an evaluation of the design in terms of power consumption and silicon real estate. The design and integration of a common-source amplifier illustrate the appropriateness of the proposed methodology.
A measurement procedure is developed specifically to characterize the phase noise of low Q, relatively unstable free-running oscillators. The phase noise performance of a VCO is evaluated theoretically using nonlinear...
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ISBN:
(纸本)0780336941
A measurement procedure is developed specifically to characterize the phase noise of low Q, relatively unstable free-running oscillators. The phase noise performance of a VCO is evaluated theoretically using nonlinear computer aided design (CAD) tool and experimentally using phase noise measurement system. General procedure and equipment setup is introduced. Effect of power supply on the phase noise is illustrated.
In this paper a new design strategy used to implement low switching noise digital circuits is presented. The switching noise reduction is achieved by controlling the shape of the switching current waveform of the CMOS...
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An improved Centers of Gravity (CG) algorithm is presented for circuit yield optimization or for the well-known design Centering (DC) problem. The CG algorithm is based on the estimation of circuit yield and CG of pas...
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ISBN:
(纸本)0780336941
An improved Centers of Gravity (CG) algorithm is presented for circuit yield optimization or for the well-known design Centering (DC) problem. The CG algorithm is based on the estimation of circuit yield and CG of pass and fail sampled points. A new type of estimator and the Latin Hypercube Sampling (LHS) scheme are proposed in order to improve the estimation accuracy with the same computational time. Simulation results have shown a good agreement with the theoretical basis.
The implementation of complex electronicsystems wing High Density Packaging (HDP) technologies requires an IC-like "first-time right" design approach, as rework and prototyping for such technologies fan be ...
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ISBN:
(纸本)081868433X
The implementation of complex electronicsystems wing High Density Packaging (HDP) technologies requires an IC-like "first-time right" design approach, as rework and prototyping for such technologies fan be extremely expensive. On the other hand, most Multichip Module (MCM) and HDP technologies have not reached a mature stage yet. Highly integrated and versatile MCM design environments, able to provide an automated design data flow and to cope with the required flexibility, are therefore a necessity. Available MCM CAD tools are adaptation of PCB rook and cannot provide the required features. This paper shows the current limitations front a general viewpoint and outlines a minimum set of features an optimised MCM design environment should offer. It describes also the development of an integrated design environment, tailored for MCM-D technologies.
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