In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique whic...
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In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior.
A novel design technique for a high-speed, high-accuracy voltage-follower is presented. The design is based on a floating negative-feedback technique which results in the commonly encountered trade-off between speed a...
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A novel design technique for a high-speed, high-accuracy voltage-follower is presented. The design is based on a floating negative-feedback technique which results in the commonly encountered trade-off between speed and accuracy being released. Details of the design principles are explained and a practical design example is described which is shown to exhibit simultaneously very high speed and very high accuracy.
This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in...
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This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range.
In this paper the design of a multiple feedback FLF log-domain filter is presented by means of the Bernoulli cell-based "log-domain state space" differential equations. Confirming HSPICE simulation results a...
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In this paper the design of a multiple feedback FLF log-domain filter is presented by means of the Bernoulli cell-based "log-domain state space" differential equations. Confirming HSPICE simulation results are presented.
In this paper, we present a design of an analogue fuzzy inference processor with emphasis on the simplicity of architecture, circuitry and implementation. A brief overview of fuzzy inference processor building blocks ...
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In this paper, we present a design of an analogue fuzzy inference processor with emphasis on the simplicity of architecture, circuitry and implementation. A brief overview of fuzzy inference processor building blocks suitable for hardware implementation using analogue Complementary Metal Oxide Semiconductor (CMOS) techniques is presented. Techniques for generalising the design into an n-rule, n-input fuzzy processor have been established. The design of an analogue fuzzy processor with 4-rule aggregation is discussed, based on a standard 2 /spl mu/m N-well process.
A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampli...
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A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in 0.5 /spl mu/m CMOS technology. Measurements show 10 bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW at 3 V power dissipation.
Since random device/process variations do not scale down with feature size or supply voltage, statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at level...
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Since random device/process variations do not scale down with feature size or supply voltage, statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. This is particularly true for low voltage analog ICs. This paper presents a robust design of a low voltage square-law CMOS composite cell, using statistical VLSI design tools. The Response Surface Methodology and design of Experiment techniques were used as statistical tools. This paper shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.
A new concept for correcting errors in digital code is presented. For this purpose a programmable cellular nonlinear network can be used. To achieve high operation speed the high gain output nonlinearity is used. Posi...
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A new concept for correcting errors in digital code is presented. For this purpose a programmable cellular nonlinear network can be used. To achieve high operation speed the high gain output nonlinearity is used. Positive range nonlinearity is combined to the high gain in order to achieve robust operation. The programmability of the network is reduced to only those coefficients actually needed in the processing to further increase the processing speed. An example of this coding scheme is given where the "bubbles" present at the thermometer code generated by a fast flash AID-converter are removed. For this correction operation simulations are given.
In this paper an approach to find two approximate poles for high speed interconnect design is presented. The approach overcomes the instability problem associated with Pade approximation. These two poles are used for ...
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In this paper an approach to find two approximate poles for high speed interconnect design is presented. The approach overcomes the instability problem associated with Pade approximation. These two poles are used for rapid evaluation of line parameter changes. Since transmission line system is a stiff system with some poles of small magnitude and some poles of large magnitude, in general, it is impossible to match the simulated waveform with the calculated waveform using a small number of poles. The objective here is to evaluate efficiently the effect of parameter changes in our optimization process. Numerical examples show that the proposed approach can meet our objective.
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