A new algorithm is given that converts a reduced representation of Boolean functions in the form of disjoint cubes to unnormalized paired Haar spectra for systems of incompletely specified Boolean functions. Since the...
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A new algorithm is given that converts a reduced representation of Boolean functions in the form of disjoint cubes to unnormalized paired Haar spectra for systems of incompletely specified Boolean functions. Since the known algorithms that generate unnormalized Haar spectra always start from the truth table of Boolean functions the method presented computes faster with a smaller computer memory. The method is extremely efficient for such Boolean functions that are described by only few disjoint cubes and it allows the calculation of only selected spectral coefficients, or all the coefficients can be calculated in parallel.
Multiple power saving methods were applied to a video processor for color digital video and still cameras. Architectural level methods failed to save power: asynchronous design, dynamic voltage scaling, bus switching ...
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ISBN:
(纸本)9781581130591
Multiple power saving methods were applied to a video processor for color digital video and still cameras. Architectural level methods failed to save power: asynchronous design, dynamic voltage scaling, bus switching minimization, pipeline stage merging, reduction of switching times and clock gating. However changing the algorithm to work on pixel differences yielded 3-15% power reduction in typical cases.
Two wideband current-mode absolute value, or precision full-wave rectifier (PFWR), circuits have been designed and developed. They are transistor level based designs, ideally suited for ASIC realisation. The two diffe...
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Two wideband current-mode absolute value, or precision full-wave rectifier (PFWR), circuits have been designed and developed. They are transistor level based designs, ideally suited for ASIC realisation. The two different, architecture circuits are described. In the first design a comparator is used to control a current-steering circuit to achieve the required unipolar output response. The topology of the circuit exhibits high speed performance with minimum transients. The second design is a development from the first. The circuit has lower overall complexity and provides enhanced performance. It is based on an emitter-coupled common-collector, with a NPN Quasi-Darlington dynamic buffer. Both techniques show promising performance in terms of operating speed.
The operation and design aspects of a receiver with a subsampling mixer are discussed at system level. A novel technique that improves the noise performance of CMOS subsamplers is proposed. The sampling frequency with...
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The operation and design aspects of a receiver with a subsampling mixer are discussed at system level. A novel technique that improves the noise performance of CMOS subsamplers is proposed. The sampling frequency with the proposed structure is fundamentally limited by the speed of the clock generator instead of the hold amplifier as is the case in previously reported subsamplers. A 300 MHz test sampler which is designed to be integrated together with a 1.8 GHz LNA is described.
In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determi...
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In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency: (i) optimization to a single modulation index point, and (ii) optimization to a range of modulation indices. For the design of an output stage with optimum power efficiency (and small IC area), we recommend the waffle layout realization optimized to a range of modulation indices. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.
This paper describes how the Bruton transformation facilitates the development of an efficient design methodology for switched-current elliptic lowpass wave filters. Wave models for the design methodology including fr...
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This paper describes how the Bruton transformation facilitates the development of an efficient design methodology for switched-current elliptic lowpass wave filters. Wave models for the design methodology including frequency dependent negative resistance (FDNR) component, capacitive source and capacitive load are presented. The proposed design technique offers a significant reduction in the filter transistor count. For example, a 7th order lowpass elliptic filter utilises 20% less delay elements and 16% less current mirrors when compared with a recently reported design technique. This is achieved by having a filter structure with a number of resistors and simplified series adapters. Simulated results based on a typical CMOS process for a lowpass elliptic filter with a cutoff frequency of 100 kHz and a sampling frequency of 1 MHz are included.
In this paper the efficient implementation of discrete multi-wavelet transforms is examined. These transforms can be used for image coding. The presented architecture is based on lattice structures and computationally...
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In this paper the efficient implementation of discrete multi-wavelet transforms is examined. These transforms can be used for image coding. The presented architecture is based on lattice structures and computationally efficient CORDIC-based /spl mu/-rotations. An exemplary VLSI implementation for a multiwavelet-based lapped orthogonal transform is presented.
A 2-GHz 'all transistor' LNA and a downconversion mixer have been implemented with a standard digital 0.5-/spl mu/m CMOS process. The LNA has been measured to have a noise figure of 5.4 dB and a 8.3-dB gain at...
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A 2-GHz 'all transistor' LNA and a downconversion mixer have been implemented with a standard digital 0.5-/spl mu/m CMOS process. The LNA has been measured to have a noise figure of 5.4 dB and a 8.3-dB gain at 2.0 GHz. The Gilbert-type downconversion mixer with a 0-dB conversion gain to a differential 100-/spl Omega/ load and DSB noise figure of 11 dB has been measured. These processed circuits demonstrate the capability of submicron CMOS technology for high frequency applications.
Mutual relations between arithmetic and unnormalized Haar functions are stated. The new relations allow one to calculate directly arithmetic spectrum from unnormalized Haar spectrum and vice versa without the necessit...
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Mutual relations between arithmetic and unnormalized Haar functions are stated. The new relations allow one to calculate directly arithmetic spectrum from unnormalized Haar spectrum and vice versa without the necessity of obtaining the original function. Since both arithmetic and Haar spectra are used widely in many applications, the presented equations should further enhance the scope of their applications.
A 2.4 GHz frequency-hopped RF transmitter IC has been designed and implemented in a 0.5 /spl mu/m CMOS. This frequency hopped spread spectrum (FH/SS) transmitter is intended for use in a wide variety of indoor/outdoor...
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A 2.4 GHz frequency-hopped RF transmitter IC has been designed and implemented in a 0.5 /spl mu/m CMOS. This frequency hopped spread spectrum (FH/SS) transmitter is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 2.4-2.4835 GHz ISM frequency band. The transmitter is capable of frequency and phase modulation. The key elements in the transmitter are: a quadrature direct digital synthesizer, digital-to-analog converters, low-pass filters, upconversion mixers and 90/spl deg/ phase splitter.
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