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A power optimization method considering glitch reduction by gate sizing 98

A power optimization method considering glitch reduction by ...

引用

International symposium on Low Power electronics and design (ISLPED)

作者： M. Hashimoto H. Onodera K. Tamaru Department of Communications and Computer Engineering Kyoto University Japan

ISBN: (纸本)9781581130591

We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and a device gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 /spl mu/m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2% on average and by 63.4% maximum. This results in the reduction of total transitions by 12.8% on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4% on average and by 15.7% maximum further from the minimum-sized circuits.

关键词： Optimization methods circuits Power dissipation Delay Timing Cost function Permission Computational efficiency Power engineering computing Power engineering and energy

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Power dissipated by CMOS gates driving lossless transmission lines 98

Power dissipated by CMOS gates driving lossless transmission...

引用

International symposium on Low Power electronics and design (ISLPED)

作者： Y.I. Ismail E.G. Friedman J.L. Neves Department of Electrical Engineering University of Rochester Rochester NY USA IBM Microelectronics East Fishkill NY USA

ISBN: (纸本)9781581130591

The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with AS/X simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. Therefore, the total power consumption is expected to decrease as inductance effects becomes more significant as compared to an RC model of the interconnect.

关键词： Propagation losses Power transmission lines Distributed parameter circuits Superconducting transmission lines RLC circuits Inductance Semiconductor device modeling Integrated circuit interconnections Wires Impedance

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Performance analysis of low oversampling ratio sigma-delta noise shapers for RF applications

Performance analysis of low oversampling ratio sigma-delta n...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： A. Gothenberg H. Tenhunen Department of Electronics Electronic System Design Royal Institute of Technology Kista Sweden

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for 4th-order cascaded noise shaper architectures for baseband front-ends and show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path.

关键词： Performance analysis Delta-sigma modulation Signal to noise ratio Baseband Signal processing Base stations Signal generators Bandwidth Very large scale integration Multi-stage noise shaping

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A 50 Mhz 5/sup TH/ order elliptic LP-filter using current mode Gm-C topology

A 50 Mhz 5/sup TH/ order elliptic LP-filter using current mo...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M. Kosunen K. Koli K. Halonen Electronic Circuit Design Laboratory Helsinki University of Technology Finland

A 50 Mhz 5th order elliptic LP-filter with current mode Gm-C topology has been designed for 0.5 /spl mu/m CMOS process and 3.3 V supply voltage. A low distortion level has been achieved by using dynamic biasing as a linearization principle. In order to further reduce the level of distortion, scaling for minimum distortion has been done. The effect of poles caused by parasitic capacitances has been canceled with phase lag compensation resistances realized with transistors biased in the saturation region in order to achieve high adjustability. With this topology the level of third order harmonic approximately -55 dBc with 500 /spl mu/A/sub pp/ input current has been achieved. The simulated dynamic range of the filter is 60 dB and it has power dissipation of 91 mW.

关键词： Voltage Low pass filters Frequency CMOS technology Power harmonic filters Transconductance Circuit topology Power dissipation Distortion Variable structure systems

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Computationally fast lattice bilinear digital ladder filters with comparison to circulator WDFs

Computationally fast lattice bilinear digital ladder filters...

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ieee International symposium on circuits and systems (ISCAS)

作者： L. Harnefors J. Holmberg M. Sollander S. Signell Department of Electrical Engineering Mälardalen University Vasteras Sweden Ericsson Radio Systems AB Stockholm Sweden

This paper considers a modified variant of the lossless digital integrator lattice filter structure, which is called a lattice bilinear digital ladder filter (BDLF). It is shown that the structure easily can be modified so that the critical loop reduces from two multipliers to one. This has the potential of significantly improving the computational speed when the filter is implemented directly in hardware. Two test filters of the modified BDLF structure are compared to three-port circulator lattice wave digital filters (WDF), which also have critical loops of only one multiplier. It is shown that for the test filters, the BDLF realizations are similar to the WDF realizations regarding multiplier wordlength requirements, while they are superior regarding quantization noise and structural complexity.

关键词： Lattices Digital filters Quantization Testing Delay Flow graphs Noise level electronic mail Hardware Signal design

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A DS-CDMA receiver using exponentially weighted despreading waveforms

A DS-CDMA receiver using exponentially weighted despreading ...

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ieee International symposium on circuits and systems (ISCAS)

作者： Yuejin Huang Tung Sang Ng Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong China

This paper presents a DS-CDMA receiver using exponentially weighted despreading waveforms (WDW). The chip weighting waveforms are designed for the purpose of multiple access interference (MAI) rejection by emphasizing the transitions of the received signal of interest. The WDW is determined only by one parameter, which leads to easy tuning of the WDW in practice to achieve the best performance. As a result, we show that the proposed receiver can reject MAI without knowing co-user's spreading codes, timing, and phase, and hence increase system capacity. Analysis and numerical results show that the proposed receiver outperforms the conventional receiver especially when MAI is significant. Finally, a discussion on the effect of bandlimited spreading signals is also given on the practical implications of the proposed technique.

关键词： Multiaccess communication Multiple access interference Integral equations Random variables Transmitters AWGN Signal design Timing Power control Power system modeling

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A simple CMOS digital controlled oscillator with high resolution and linearity

A simple CMOS digital controlled oscillator with high resolu...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Cheuk-Him To Cheong-Fat Chan O. Chiu-Sing Choy Department of Electronic Engineering Chinese University of Hong Kong Sha Tin Hong Kong China

This paper presents a new DCO (digital controlled oscillator) circuit which has a very simple structure with high resolution and linearity. For example, a six bit DCO only requires seventeen MOS transistors. As a result of the simple structure, the new DCO also consumes less power compared to other DCO designs. Another added feature of this new design is that the output signal can be phase-locked to an external input signal. A four bit DCO test circuit was fabricated with a 0.7 /spl mu/m CMOS technology. The test circuit has a die size of 0.024 mm/sup 2/ and an operating frequency range from 13 MHz to 50 MHz.

关键词： Digital control Digital-controlled oscillators Linearity Circuit testing Frequency Delay CMOS technology Inverters MOSFETs Voltage-controlled oscillators

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design of a scan line image processor chip

Design of a scan line image processor chip

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Hyunman Chang Soohwan Ong Changhee Lee M.H. Sunwoo School of Electronic and Computer Eng Ajou University Suwon South Korea

This paper describes a linear array image processor chip called the SliM-II image processor. The chip has 64 processing elements (PEs) connected by a linear array. In contrast to existing array processors, each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU, a data I/O, and an inter-PE communication operations simultaneously in an instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel data load/store between the register file and on-chip memory as in DSP chips. The SliM-II chip has been implemented, which contains about 1.5 million transistors in a 13.2/spl times/13.0 mm/sup 2/ die size and the package type is 208 pin PQ2. The performance estimation shows a significant improvement compared with existing array processors.

关键词： Decoding Adders Image processing Registers Streaming media Convolution Digital signal processing chips Packaging Surveillance Inspection

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The energy complexity of register files 98

The energy complexity of register files

引用

International symposium on Low Power electronics and design (ISLPED)

作者： V. Zyuban P. Kogge Computer Science & Engineering Department University of Notre Dame IN USA

ISBN: (纸本)9781581130591

Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue. The actual access energy costs depend greatly on the register file circuitry used. This paper compares various RF circuitry techniques for their energy efficiencies, as a function of architectural parameters such as the number of registers and the number of ports. The port priority selection technique was found to be the most energy efficient. The dependence of register file access energy upon technology scaling is also studied. However, as this paper shows, it appears that none of these will be enough to prevent centralized register files from becoming the dominant power component of next-generation superscalar computers, and alternative methods for inter-instruction communication need to be developed. Split register file architecture is analyzed as a possible alternative.

关键词： Registers Radio frequency Logic circuits Power system modeling Permission Buffer storage Computer science Modems Costs

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Noise in self-timed and synchronous implementations of a DSP

Noise in self-timed and synchronous implementations of a DSP

引用

ieee Radio and Wireless symposium (RWS formerly RAWCON)

作者： W.A. Lien P. Day C. Farnsworth R. Glibbery D.L. Jackson J. Liu N.C. Paver J. Chappel L. Kozma Cogency Technology Inc. Toronto ONT Canada

This paper proposes the use of self-timed design as an elegant and cost effective solution to control noise. The importance of reducing the high frequency components of the switched current is demonstrated from a review of noise sources in electronic systems. The paper includes a comparison between synchronous and self-timed systems based on the implementation of a DSP and clearly demonstrates the benefits of self-timed design.

关键词： Digital signal processing Circuit noise Noise reduction Acoustical engineering Switching circuits Clocks CMOS logic circuits Protocols Routing Logic circuits

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