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Morphological signal adaptive median filter for still image and image sequence filtering

Morphological signal adaptive median filter for still image ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： S. Tsekeridou C. Kotropoulos I. Pitas Department of Informatics Aristotle University of Thessaloniki Thessaloniki Greece

A novel extension of the classical signal-adaptive median filter (SAM) is proposed in this paper, namely the morphological signal-adaptive median filter (MSAM). Three modifications are introduced in the SAM filter aiming at: (1) enhancing the SAM impulse detection mechanism so that it also detects randomly-valued impulses, (2) employing an anisotropic window adaptation based on binary morphological erosions/dilations with predefined structuring sets and (3) extending its design for its application to image sequences as well. Its performance has been tested for noise suppression in both still images and image sequences. Its robustness against a wide variety of noise distributions as well as its superiority to the classical SAM filter are proved judging from both objective (SNR, MAE) and subjective (perceived image quality) criteria.

关键词： Adaptive filters Image sequences Additive white noise Filtering Signal to noise ratio Additive noise Smoothing methods Pixel Informatics electronic mail

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A low power SRAM using auto-backgate-controlled MT-CMOS 98

A low power SRAM using auto-backgate-controlled MT-CMOS

引用

International symposium on Low Power electronics and design (ISLPED)

作者： K. Nii H. Makino Y. Tujihashi C. Morishima Y. Hayakawa H. Nunogami T. Arakawa H. Hamano Mitsubishi Electr. Corp. Hyogo Japan Mitsubishi Electric Corporation Limited Itami Hyogo Japan Tokushima Bunri University Shido Kagawa Japan

ISBN: (纸本)9781581130591

We have proposed a low power SRAM using an effective method called "ABC-MT-CMOS". It controls the backgates to reduce the leakage current when the SRAM is not activated (sleep mode) while retaining the data stored in the memory cells. We also adopted a "CSB Scheme" which clamps both the source lines of the memory cell array and the bit lines. We designed and fabricated test chips containing a 32 K-bit gate array SRAM. The experimental results show that the leakage current is reduced to 1/1000 in sleep mode. The active power is 0.27 mW/MHz at 1 V, which is a reduction of 1/12 of a conventional SRAM with a 3.3 V.

关键词： Random access memory Leakage current Threshold voltage Permission Clamps Testing Low voltage Charge pumps CMOS memory circuits Latches

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Computational complexity analysis of set-bin-packing problem

Computational complexity analysis of set-bin-packing problem

引用

ieee International symposium on circuits and systems (ISCAS)

作者： T. Izumi T. Yokomaru A. Takahashi Y. Kajitani Department of Electrical and Electronic Engineering Tokyo Institute of Technology Meguro Tokyo Japan

Given a set of items and a set of bins of the same capacity, the Set-Bin-Packing Problem (SEP) is to pack all the items into the bins where each item is associated with a set and a bin can contain items as long as the number of distinct elements in the union of the sets does not exceed the capacity. One of applications is in FPGA technology mapping, which is our initial motivation. In FPGA terminology, an item, an element in an item, a bin, capacity correspond to a gate, an input signal of a gate, an LUT, and the number of input terminals of an LUT. In this paper, the computational complexity of SEP is studied with respect to three parameters; the number of input terminals of an LUT, the upper bound of the number of input signals of a gate, and the upper bound of the number of fanout gates of a signal, respectively. Our result reveals that SEP remains NP-hard for small values of these parameters. The results are summarized on a 3D map of computational complexities with respect to these three parameters.

关键词： Computational complexity Table lookup Field programmable gate arrays Upper bound Very large scale integration circuits Terminology Containers Algorithm design and analysis Heuristic algorithms

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Intelligent gripper using low cost industrial sensors

Intelligent gripper using low cost industrial sensors

引用

ieee International symposium on Industrial electronics (ISIE)

作者： N.S. Tlale R. Mayor G. Bright Department of Mechanical Engineering University of Natal Durban South Africa

Intelligent generic grippers using low-cost electronics can be used for part identification when attached to a robot end effector. The versatility of a generic gripper makes it suitable for the automated population of printed circuit boards (PCBs). electronic component assembly onto printed circuit boards was implemented by means of the reverse engineering concept commonly used in flexible manufacturing systems. The process of component assembly was made more efficient using a generic gripper as opposed to using individual dedicated grippers. The conceptual design of the gripper was based on the group technology approach that required the manipulation of electronic components. The automated assembly of the PCB was a successful test of the grippers capabilities. The integration of the generic gripper with the low-cost hardware and software required for reverse engineering could increase the efficiency and flexibility of automated assembly stations. The work details the design, control, fabrication, implementation, procedures and results of the generic gripper for electronic component assembly.

关键词： Intelligent sensors Grippers Costs Intelligent robots electronic components Flexible printed circuits Robotic assembly Reverse engineering Service robots Robot sensing systems

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Fast high-level power estimation for control-flow intensive design 98

Fast high-level power estimation for control-flow intensive ...

引用

Proceedings of the 1998 international symposium on Low power electronics and design

作者： Kamal S. Khouri Ganesh Lakshminarayana Niraj K. Jha Department of Electrical Engineering Princeton University Princeton NJ

ISBN: (纸本)9781581130591

In this paper, we present a power estimation technique for control-flow intensive designs that is tailored towards driving iterative high-level synthesis systems, where hundreds of architectural trade-offs are explored and compared. Our method is fast and relatively accurate. The algorithm utilizes the behavioral information to extract branch probabilities, and uses these in conjunction with switching activity and circuit capacitance information, to estimate the power consumption of a given *** test our algorithm using a series of experiments, each geared towards measuring a different indicator. The first set of experiments measures the algorithm's accuracy when compared to the actual circuit power. The second set of experiments measures the average tracking index, and tracking index fidelity for a series of architectures. This index measures how well the algorithm makes decisions when comparing the relative power consumption of two architectures contending as low-power *** indicate that our algorithm achieved an average estimation error of 11.8% and an average tracking index of 0.95 over all examples.

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Power electronics Building Blocks and potential power modulator applications

Power Electronics Building Blocks and potential power modula...

引用

ieee symposium Power Modulator

作者： T. Ericsen A. Tucker Code 334 Office Of Naval Research Arlington VA USA Code 334 Office Of Naval Research Arlington VA

Power electronic Building Blocks (PEBBs) are power processors. A PEBB is not a specific semiconductor material, not a device, nor a circuit topology. It is the search for the common electrical, mechanical and thermal denominators of all these, allowing integration of all these technologies. It is not; "one size fits all". There will be several blocks that will fit together to perform the majority of everyday power electronic jobs. Like a set of children's interlocking blocks, PEBBs will be a rational and simple set of blocks and procedures that most any designer or architect can use to build electrical systems. The Office of Naval Research (ONR) is developing Power electronic Building Blocks to achieve: increased power density, "user friendly" design ("plug and play" power modules), and multi-functionality. Digital controls, integrated with higher frequency and more robust power circuits, enable modular power systems with lower size, weight, and cost-while increasing performance. Although the day when solid-state will replace tubes in high-power modulator applications is still in the future, many near-term opportunities exist for PEBBs and associated technologies. This paper presents requirements, opportunities and issues for standardized power modules. First, an overview of the PEBB program is given. Then, opportunities are examined for technologies developed by the PEBB program.

关键词： Power electronics Multichip modules Semiconductor materials Circuit topology Digital control Frequency Robust control Power systems Solid state circuits Integrated circuit technology

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Solid-state pulsed power systems

Solid-state pulsed power systems

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ieee symposium Power Modulator

作者： M.P.J. Gaudreau J. Casey T. Hawkey J.M. Mulvaney M.A. Kempkes Diversified Technologies Inc. Bedford MA USA

High energy physics, particle accelerators, and commercial semiconductor and metal treatment processes require reliable, high power, variable pulsewidth, flat top, high voltage pulses at high power. New processes for food sterilization, waste treatment, pollution control, and medical diagnostics and treatment are also being developed which also require high power, high voltage pulsed power. The technology needed to enable solid state high voltage, high power systems is now available. It has been demonstrated that solid state electronics can bring strong benefits to high voltage, high power systems design including: (a) efficiency>90%; (b) low component cost; (c) very high average and pulse power densities (>10 MW/m/sup 3/ peak power); (d) multimegawatt-level average power; (e) voltage levels from 1-150 kV; (f) average current levels from 10 A to 1200 A; (g) pulse repetition frequencies (PRFs) of 30 kHz and above (up to 400 kHz demonstrated); (h) rise and fall times as low as 250 ns; (i) variable pulse lengths (1 /spl mu/S to DC); and (j) high reliability.

关键词： Pulse power systems Solid state circuits Power system reliability Voltage Medical treatment Industrial power systems Linear particle accelerator Semiconductor device reliability Space vector pulse width modulation Pollution control

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SIP-Spice Intranet Package

SIP-Spice Intranet Package

引用

ieee International symposium on Industrial electronics (ISIE)

作者： B. Wilamowski J. Regnier A. Malinowski Department of Electrical Engineering University of Wurzburg Laramie WY USA

Computer network communications have become a popular and efficient means of computing. Most companies and research institutions use networks to some extent on a regular basis. This paper demonstrates the capability of computer-aided design (CAD) through computer networks. There are several benefits that make networked CAD tools desirable. A networked application can be used remotely through any network connection. Any operating system can be used to access a networked application, making the application operating system independent. Also the application can be made to run on a pay-per-use basis if licensing is desired, and much less installation time and configuration time is required because the application is located on one central machine. The Spice Intranet Package (SIP) is demonstrated as an example of such a networked CAD application. This particular application allows users to run Spice simulations and view graphical analysis of electronic circuits through a network connection using a Web browser. The SIP application has many options that include simulation and analysis of Spice files, graphical analysis of data, online editing of Spice files, passwords with separate file areas for each user, and a user friendly graphical user interface.

关键词： Application software Computer networks design automation Operating systems Analytical models Circuit simulation Licenses electronics packaging Packaging machines Circuit analysis

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Symbolic analysis of nearly sinusoidal oscillators

Symbolic analysis of nearly sinusoidal oscillators

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1997 ieee International symposium on circuits and systems (ISCAS 97) - circuits and systems in the Information Age

作者： Buonomo, A DiBello, C DiGenio, P Universita' di Salerno Salerno Italy

ISBN: (纸本)078033583X

We show that the nonlinear analysis of nearly sinusoidal oscillators can be performed by a very simple symbolic program, whereby the periodic oscillation as well as its frequency is determined in symbolic form in terms of both linear and nonlinear circuit parameters. The program is an useful design tool, as it enables the harmonic content and the frequency sensitivity to circuit parameters to be obtained in analytic form.

关键词： Oscillators (electronic)

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design of class DE high-efficiency tuned power oscillator

Design of class DE high-efficiency tuned power oscillator

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1997 ieee International symposium on circuits and systems (ISCAS 97) - circuits and systems in the Information Age

作者： Matsuo, M Shinoda, K Suetsugu, T Mori, S Keio Univ Yokohama Japan

ISBN: (纸本)078033583X

A class DE high-efficiency tuned power oscillator which is based on the class DE inverter is proposed, analyzed and verified experimentally. It consists of a class DE inverter and a feedback-loop for phase matching. Theoretical conditions for optimum operation of the oscillator are formulated. The proposed oscillator is especially applicable at high frequency performance because it minimizes the power dissipated during each MOSFET turning on. The measured efficiency was over 90 % at 2MHz 3W.

关键词： Oscillators (electronic)

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