An optimum signal in the form of a linearly-increased frequency-hopped uniform pulse train is derived and analyzed. This signal possesses some good wideband ambiguity properties that are useful for many practical appl...
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An optimum signal in the form of a linearly-increased frequency-hopped uniform pulse train is derived and analyzed. This signal possesses some good wideband ambiguity properties that are useful for many practical applications. In this paper, the proposed signal is specifically used as the source input in the context of target localization in which time delay and Doppler stretch estimation based on the wideband ambiguity function are required. A significant improvement in terms of estimation accuracy is obtained.
An adaptive nonlinear RLS algorithm for robust filtering in impulse noise is presented. The analysis of the mean and mean-square behaviours is carried out and verified by simulation. It is shown that the new algorithm...
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An adaptive nonlinear RLS algorithm for robust filtering in impulse noise is presented. The analysis of the mean and mean-square behaviours is carried out and verified by simulation. It is shown that the new algorithm can provide a robust performance against impulse noise and outperform the LMS counterpart and the RLS algorithm particularly when there is impulse noise.
An integrated cable equalizer circuit for 150 Mbit/s data transmission is described. The DATA-signal comes from a 75 /spl Omega/ cable, which has nonconstant frequency dependent attenuation. For that reason the signal...
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An integrated cable equalizer circuit for 150 Mbit/s data transmission is described. The DATA-signal comes from a 75 /spl Omega/ cable, which has nonconstant frequency dependent attenuation. For that reason the signal amplitude at the output of the equalizer is controlled with an Automatic Gain Control (AGC) loop. The circuit is implemented with a 1.2 /spl mu/m BiCMOS technology.
We present an architecture evaluation system which aids designer optimization of the datapath configuration and the instruction set of embedded custom DSPs. Given a datapath structure, it evaluates the performance in ...
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We present an architecture evaluation system which aids designer optimization of the datapath configuration and the instruction set of embedded custom DSPs. Given a datapath structure, it evaluates the performance in terms of an estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicitly specifying the instruction format. Thus, designers can evaluate the performance of architectural variations in the early design stage. We applied the system to some actual designs of signal processors. We show some applications of the system to actual signal processors.
This paper presents a physics-based model for the MOS transistor, suitable for circuit design and simulation and valid from weak to strong inversion. Each static or dynamic characteristic is accurately described by a ...
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This paper presents a physics-based model for the MOS transistor, suitable for circuit design and simulation and valid from weak to strong inversion. Each static or dynamic characteristic is accurately described by a single-piece function of two saturation currents.
An efficient design method is introduced for optimizing polynomial-based FIR filters with adjustable fractional delay. Given the passband region, the filter parameters are optimized to minimize in the passband the wor...
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An efficient design method is introduced for optimizing polynomial-based FIR filters with adjustable fractional delay. Given the passband region, the filter parameters are optimized to minimize in the passband the worst-case phase delay deviation from the desired value (the maximum deviation for fractional delays between zero and unity) subject to a given worst-case amplitude deviation from unity in the passband. It is shown that the filter with fractional delay equal to half determines the lower limit for the achievable amplitude distortion. Because the filters under consideration are polynomial-based, they can be efficiently implemented using the modified Farrow structure introduced by the authors.
DC-15 GHz 1.7 Volts and DC-30 GHz 3 Volts wideband amplifiers and 40 GHz, 3 Volts narrowband amplifier with bandwidth of about 200 MHz have been designed and fabricated in Hughes Research Laboratories' InP-HBT tec...
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DC-15 GHz 1.7 Volts and DC-30 GHz 3 Volts wideband amplifiers and 40 GHz, 3 Volts narrowband amplifier with bandwidth of about 200 MHz have been designed and fabricated in Hughes Research Laboratories' InP-HBT technology. The 15 GHz amplifier is based on a differential stage with emitter degeneration resistors and the 30 GHz and 40 GHz amplifiers utilize trans-impedance, trans-admittance structures.
EMC is practiced in efficient operation, maintenance of reliability and safety of various electronicsystems used in military and civil sectors and medicare. In the Indian context, it is essential to make indigenous p...
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EMC is practiced in efficient operation, maintenance of reliability and safety of various electronicsystems used in military and civil sectors and medicare. In the Indian context, it is essential to make indigenous products acceptable and competitive in domestic and international markets, especially in the European union, by designing reliable equipment. This paper addresses the following: (a) quality control for VLSI based systems through good EMC design practices, (b) sub-system module packaging, (c) hardening of electronic components for EMC and reliability, (d) protection of transient effects on digital circuits, (e) component-value-optimisation and (f) EMC maintenance considerations. The measurement results complying with the FCC specifications (class B) are included for a microprocessor subsystem.
The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can...
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The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.
This paper extends the Weighted Least Squares method to designing FIR filters capable of changing, in the real-time, one of their frequency response characteristics (group delay, the width of the passband, resonance f...
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This paper extends the Weighted Least Squares method to designing FIR filters capable of changing, in the real-time, one of their frequency response characteristics (group delay, the width of the passband, resonance frequency or any other). The filter coefficients are polynomial functions of the parameter characterising the variable feature. The computations needed in such designs can be kept at low level if the weight function in the performance criterion is separable. The advantages of the proposed approach are illustrated by a design of a Fractional Sample Delay filter with variable delay. If this filter has to meet demanding specifications then the proposed approach provides a cheaper and more effective solution than traditional approaches based on Lagrange interpolation.
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