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Achieving the enhanced reliability of electronic system by application of EMI control measures

Achieving the enhanced reliability of electronic system by a...

引用

ieee International symposium on Electromagnetic Compatibility (EMC)

作者： G.K. Deb Electronics Research and Development Centre of India Calcutta India

EMC is practiced in efficient operation, maintenance of reliability and safety of various electronic systems used in military and civil sectors and medicare. In the Indian context, it is essential to make indigenous products acceptable and competitive in domestic and international markets, especially in the European union, by designing reliable equipment. This paper addresses the following: (a) quality control for VLSI based systems through good EMC design practices, (b) sub-system module packaging, (c) hardening of electronic components for EMC and reliability, (d) protection of transient effects on digital circuits, (e) component-value-optimisation and (f) EMC maintenance considerations. The measurement results complying with the FCC specifications (class B) are included for a microprocessor subsystem.

关键词： Electromagnetic compatibility Maintenance Safety Quality control Very large scale integration electronics packaging Packaging machines electronic components Protection Digital circuits

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WLS design of variable frequency response FIR filters

WLS design of variable frequency response FIR filters

引用

ieee International symposium on circuits and systems (ISCAS)

作者： A. Tarczynski G.D. Cain E. Hermanowicz M. Rojewski School of Electronic and Manufacturing Engineering University of Westminster London UK Faculty of Electronics Telecommunications and Computer Science Technical University of Gdańsk GdaDsk Poland

This paper extends the Weighted Least Squares method to designing FIR filters capable of changing, in the real-time, one of their frequency response characteristics (group delay, the width of the passband, resonance frequency or any other). The filter coefficients are polynomial functions of the parameter characterising the variable feature. The computations needed in such designs can be kept at low level if the weight function in the performance criterion is separable. The advantages of the proposed approach are illustrated by a design of a Fractional Sample Delay filter with variable delay. If this filter has to meet demanding specifications then the proposed approach provides a cheaper and more effective solution than traditional approaches based on Lagrange interpolation.

关键词： Frequency response Finite impulse response filter Delay Least squares methods design methodology Passband Resonance Resonant frequency Polynomials Lagrangian functions

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Mixed analog-digital circuit for linear-time programmable sorting

Mixed analog-digital circuit for linear-time programmable so...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： G. Oddone S. Rovetta G. Uneddu R. Zunino DIBE-Department Biophysical and Electronic Engineering University of Genoa Genoa Italy

The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.

关键词： Analog-digital conversion circuits Sorting Very large scale integration Voltage Switches Neural networks Evolutionary computation Computational modeling Hardware

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An area and time efficient adder for multiple additions with different word-length

An area and time efficient adder for multiple additions with...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Bor-Sung Liang You-Cheng Nieh Chein-Wei Jen Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan

To calculate multiple independent additions with different word-lengths by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision frequently occur in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, the SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization.

关键词： Hardware Routing Costs Clocks Adders Delay effects Graphics Throughput electronic mail Rendering (computer graphics)

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An improved fault tolerant architecture at CMOS level

An improved fault tolerant architecture at CMOS level

引用

ieee International symposium on circuits and systems (ISCAS)

作者： C. Bolchini G. Buonanno D. Sciuto R. Stefanelli Dipartimento di Elettronlca e Informazione Politecnico di Milano Milan Italy

A previous realization of a fault tolerant architecture at CMOS level, while guaranteeing the correct behavior of the circuit both in the fault-free situation and in the presence of stuck-on faults, was characterized by a neither null nor +V/sub dd/ output voltage when faults occurred. An improved architecture is here presented, which by adding additional transistors, achieves the fault tolerance property without degrading the performance of the circuit in terms of output voltage and short circuit current.

关键词： Fault tolerance Circuit faults Voltage Semiconductor device modeling electronic mail Degradation CMOS technology design methodology Fault diagnosis Delay

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A closed-form solution for the design of complex FIR filters and its application to filter banks

A closed-form solution for the design of complex FIR filters...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Wei-Ping Zhu M.O. Ahmad M.N.S. Swamy Center for Signal Processing and Communications Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada

In this paper, the least-square design problem of complex FIR filters with arbitrary frequency response characteristics is investigated. A closed-form solution is obtained by solving the approximation problem analytically, enabling a very fast calculation of the impulse response of the filter to be designed. An application of the derived solution to QMF bank design is explored. By using the Butterworth approximation to obtain an IIR filter for the analysis part and by employing the closed-form solution to approximate a nonlinear-phase FIR filter for the synthesis part, a class of nearly perfect-reconstruction QMF bank is developed. It is shown that the mixed IIR/FIR filter bank not only has a very good reconstruction performance but also enjoys an extremely low design complexity.

关键词： Finite impulse response filter Closed-form solution Filter bank Channel bank filters Frequency response IIR filters Digital filters Application software Signal processing electronic mail

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Control of discrete-time chaotic systems using generalized predictive control

Control of discrete-time chaotic systems using generalized p...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Kwang-Sung Park Jin-Man Joo Jin-Bae Park Yoon-Ho Choi Tae-Sung Yoon Department of Electrical Engineering Yonsei University South Korea Department of Electronic Engineering Kyonggi University South Korea Department of Electrical Engineering Changwon NatE28099l University South Korea

In this study, a controller design method is proposed for controlling the discrete-time chaotic systems. The proposed method is based on generalized predictive control and uses NARMAX models as controlled models. In order to evaluate the performance of the proposed method, a proposed controller is applied to discrete-time chaotic systems, and then the control performance and initial sensitivity of the proposed controller are compared with those of the conventional model-based controller through computer simulations.

关键词： Control systems Chaos Predictive control Autoregressive processes Predictive models Nonlinear control systems Control system synthesis Programmable control Adaptive control Equations

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Efficient modulo extraction for CRT based residue to binary converters

Efficient modulo extraction for CRT based residue to binary ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： G.C. Cardarilli M. Re R. Lojacono Department of Electronic Engineering University of Roma Tor Vergata Rome Italy

RNS to binary conversion is a very critical task for an advantageous implementation of RNS based Digital Signal Processors (DSPs). This paper presents a new technique for the module extraction useful for the implementation of efficient Chinese Remainder Theorem (CRT) based converters. The method, based on the multiplication of the CRT terms by a power of two, greatly simplifies the extraction of the final modulo only requiring a look-up table access and two sums. The resulting structures appear very efficient in terms of speed and area occupancy.

关键词： Cathode ray tubes Computer architecture Hardware Digital signal processors Table lookup Error correction Digital arithmetic Signal design Digital signal processing Proposals

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design of wave-parallel computing architectures using orthogonal sequences

Design of wave-parallel computing architectures using orthog...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Y. Yuminaka Y. Sasaki Dept. of Electron. Eng. Gunma Univ. Japan Department of Electronic Engineering Faculty of Engineering Gunma University Kiryu Japan

Wave-parallel computing (WPC) architectures are proposed to address interconnection problems in massively interconnected VLSI architectures. The fundamental concepts are multiplexing of several signals onto a single line, and their wave-parallel processing without decomposition. This paper discusses the realization of a Hopfield-type fully connected neural network as an example, and shows that the WPC-based network exhibits much lower topological complexity compared with the original network.

关键词： Computer architecture Integrated circuit interconnections Very large scale integration Signal processing Neural networks Delay Concurrent computing Parallel processing Hopfield neural networks Power system interconnection

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Low voltage swing circuits for low dissipation busses

Low voltage swing circuits for low dissipation busses

引用

ieee International symposium on circuits and systems (ISCAS)

作者： G.C. Cardarilli M. Salmeri A. Salsano O. Simonelli Department of Electronic Engineering University of Roma Tor Vergata Rome Italy

Power reduction is one of the most important issues of modern VLSI design. Many analyses show that a larger quantity of power is dissipated for the communication, both inside and outside the chip. Different methodologies have been proposed to reduce such power dissipation. In this paper we consider the approach based on reduction of the voltage. In the literature this approach is based on interface circuits that make use of sophisticated technology. Moreover, these circuits are quite complex. Our efforts are devoted to developing a solution based on quite simple interface circuits implemented in conventional CMOS technology. In this paper we review the interface circuits already proposed by the authors and discuss the measurement results of a test chip. Starting from the drawbacks highlighted by these measurements, we propose new circuits based on a new technique of voltage swing reduction and present a preliminary simulation.

关键词： Low voltage CMOS technology Semiconductor device measurement Circuit testing Very large scale integration Driver circuits Circuit simulation Parasitic capacitance Integrated circuit interconnections Energy consumption

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