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Reducing hardware complexity of motion estimation algorithms using truncated pixels

Reducing hardware complexity of motion estimation algorithms...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Zhongli He M.L. Liou Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Kowloon Hong Kong China

Traditional block-matching motion estimation algorithms search motion vectors using full precision pixels, normally 8-bits-per-pixel. In this paper, we introduce an approach for block-matching motion estimation using truncated pixels. The full-search algorithm is employed for discussion. We investigate the system performance with different number of truncated bits. Simulation results show that the matching error decreases exponentially when the number of truncated bits is reduced, and the number of truncated bits of 4 can be chosen as a reasonable solution for motion vector searching. We also discovered that the average PSNR of the decoded video sequences degrades only 0.03%-2.1%, while the equivalent gate count drops 46% for many of the existing VLSI architectures!.

关键词： Hardware Motion estimation System performance Video sequences Algorithm design and analysis Computer architecture Costs Quantization Helium Decoding

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Realistic fault extraction for high-quality design and test of VLSI systems

Realistic fault extraction for high-quality design and test ...

引用

ieee International symposium on Defect and Fault Tolerance in VLSI systems

作者： F.M. Goncalves I.C. Teixeira J.P. Teiceira INESC/IST Lisboa Portugal

The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled both in Manhattan and 45/spl deg/ geometries. Higher level design data, obtained in the top-down design flow, is used for realistic fault characterization. A sliding window algorithm is extended for fault extraction of non-orthogonal geometries. An accurate critical area evaluation algorithm is proposed to compute the probability of occurrence of the defects. Over 100,000 transistor ICs are analyzed for bridging defects.

关键词： System testing Very large scale integration Circuit faults Data mining electronic design automation and methodology Circuit testing CMOS technology Information geometry BiCMOS integrated circuits Signal design

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A current-mode phase-locked loop using a log-domain oscillator

A current-mode phase-locked loop using a log-domain oscillat...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： A. Thanachayanont A. Payne S. Pookaiyaudom Department of Electrical & Electronic Engineering Imperial College of Science Technology and Medicine London UK Faculty of Engineering Mahanakom University of Technology Bangkok Thailand

This paper describes the design of a high frequency, wide tuning range and low distortion current-mode phase-locked loop. The loop is simple to tune, with independent control of centre frequency and loop bandwidth by varying bias currents. The loop employs the recently proposed current-mode 'log-domain' oscillator in a classical phase-locked loop topology to obtain these features. Simulation results, using HSPICE with Nortel 0.8 /spl mu/m BiCMOS technology, demonstrate that the current-mode phase-locked loop operates with a lock range of 3.5 MHz at a centre frequency of 50 MHz. Total harmonic distortion of the oscillator output at 50 MHz, with a peak-to-peak amplitude of 75% of the bias current, is less than 1.5% (-36 dB). The centre frequency of the phase-locked loop can be varied over several decades.

关键词： Phase locked loops Oscillators Filters Tuning Bandwidth Equations BiCMOS integrated circuits Voltage Frequency synthesizers Dynamic range

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Analysis of a hybrid defect-tolerance scheme for high-density memory ICs

Analysis of a hybrid defect-tolerance scheme for high-densit...

引用

ieee International symposium on Defect and Fault Tolerance in VLSI systems

作者： I. Koren Z. Koren Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Recent increases in the density and size of memory ICs made it necessary to search for new defect tolerance techniques since the traditional methods are no longer effective enough. Several new such schemes have been recently proposed and implemented. Due to the high complexity of these new techniques compared to the simple row and column redundancy, Monte-Carlo simulations were used to evaluate their yield enhancement. In this paper we present a yield analysis of one such new design and compare its yield to that of the traditional design.

关键词： Redundancy Random access memory CMOS technology electronic mail Production Driver circuits Contracts Costs Silicon Fuses

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A compact three-step pipelined CMOS current-mode A/D converter

A compact three-step pipelined CMOS current-mode A/D convert...

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ieee International symposium on circuits and systems (ISCAS)

作者： J.P.A. Carreira C. Dupuy J.E. Franca Atmel ES2 Rousset France Atmel Corporation Rousset France Integrated Circuit and Systems Group IST Portugal

This paper describes the architecture and circuit design of a three-step pipelined A/D converter implemented using the continuous-time current-mode technique. A transistor-only three-step architecture was used to optimize area and power dissipation while maintaining analog bandwidth and hence the effective number of bits over the full input Nyquist band. Simulation results show 8-bit accuracy with a sampling rate up to 54 MHz. The A/D converter is fabricated in a standard single poly double-metal digital 0.8 /spl mu/m CMOS process and occupies a die area of 0.38 mm/sup 2/ including input current and reference pads. The entire circuit dissipates 20 mW at 54 MHz of conversion rate while operating from a single 5 V power supply.

关键词： CMOS technology Error correction Sampling methods Pipelines Frequency conversion electronic mail CMOS process Circuit synthesis Power dissipation Bandwidth

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Real-time video vector quantization encoder using FPGA chip

Real-time video vector quantization encoder using FPGA chip

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ieee International symposium on circuits and systems (ISCAS)

作者： C.F. Cheung C.K. Chan Dept. of Electron. Eng. City Univ. of Hong Kong Hong Kong Department of Electronic Engineering City University of Hong Kong Kowloon Hong Kong China

Vector Quantization has becoming a viable approach in the coding of speech and image data in the last decade. The regularity and simplicity of the VQ process make it feasible for low cost and low complexity hardware implementation, while maintaining an acceptable level of perceived image quality at relatively low bit rate. For real-time video VQ encoder, in order to process the high-speed image data stream, most people are still heavily reliant on systolic and VLSI implementations. This has become a major obstacle in the maturity of today's hardware VQ encoder. Such design processes are expensive, relatively time consuming, and most importantly, inflexible. In this paper, a real-time video VQ encoder using FPGA chip for implementation is presented. Such design process is low cost, relatively fast, and flexible. The finished VQ encoder chip is running at a system clock of 5 MHz and capable of encoding color SIF images at 30 fps.

关键词： Vector quantization Field programmable gate arrays Image coding Costs Hardware Process design Speech coding Image quality Bit rate Streaming media

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Low-voltage rail-to-rail CMOS differential difference amplifier

Low-voltage rail-to-rail CMOS differential difference amplif...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Chung-Chih Hung M. Ismail K. Halonen V. Porra Analog VLSI Laboratory Department of Electrical Engineering Ohio State Uinversity Columbus OH USA Electronic Circuit Design Laboratory Department of Electrical Engineering Helsinki University of Technology Espoo Finland

This paper introduces a low-voltage rail-to-rail wide range CMOS Differential Difference Amplifier (DDA). The input stage of this DDA comprises two rail-to-rail VI converters with large signal handling capability. In each V-I converter, an N-type converter cell is connected in parallel with its P-type counterpart cell in order to cover all the operating range of the common-mode input voltage. Its constant transconductance is achieved through the use of two maximum-current selecting circuits and an output substraction stage. Simulation results of the DDA with 3 V supply show that the DDA has a rail-to-rail constant input transconductance, a rail-to-rail output swing, 66 dB open-loop gain, and a 2.2 MHz bandwidth with C/sub L/=30 pF and R/sub L/=250 /spl Omega/. Low-voltage DDA-based circuits, such as an adder/substractor and an integrator, are given in this paper. They constitute basic blocks of modern low-voltage analog signal and information processing systems.

关键词： Differential amplifiers Rail to rail amplifiers Rail to rail inputs Transconductance Rail to rail outputs Voltage Circuit simulation Gain Bandwidth Adders

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A 2000 bps LPC vocoder based on multiband excitation

A 2000 bps LPC vocoder based on multiband excitation

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ieee International symposium on circuits and systems (ISCAS)

作者： J.S. Mao Z. Chen S.C. Chan T.S. Ng K.L. Ho Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong China

This paper presents an improved mixed LPC vocoder at 2000 bps using Multi-Band Excitation analysis by a synthesis algorithm. The new vocoder determines the voiced/unvoiced characteristics harmonic by harmonic in a frame, and finds the first voiced/unvoiced transition as the cut-off frequency, which is more accurate and efficient than traditional cut-off frequency detection. The synthetic speech below the cut-off frequency is excited by a series of voiced harmonics, while the signal above the cut-off frequency is simulated by a noise source. The final output speech is the sum of these two outputs. To increase the naturalness and clearness of the synthesized speech, this model applies phase prediction and spectral enhancement in the synthesizer. It is also possible to reduce the bit rate to 1200 bps. Informal listening tests indicate that the output speech possesses higher intelligibility and quality than that of the 2.4 kbps LPC-10e standard, and is comparable with the 4.8 kbps FS1016 CELP vocoder.

关键词： Linear predictive coding Vocoders Cutoff frequency Speech synthesis Speech enhancement Algorithm design and analysis Signal synthesis Predictive models Synthesizers Bit rate

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Fully depleted CMOS/SOI device design guidelines for low power applications 97

Fully depleted CMOS/SOI device design guidelines for low pow...

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Proceedings of the 1997 international symposium on Low power electronics and design

作者： Srinivasa R. Banna Philip C. H. Chan Mansun Chan Samuel K. H. Fung Ping K. Ko Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Clear Water Bay Kowloon Hong Kong

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A real-time monitor using wavelet analysis of the Doppler heart sound for the detection of venous air embolism

A real-time monitor using wavelet analysis of the Doppler he...

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ieee International symposium on circuits and systems (ISCAS)

作者： B.C.B. Chan F.H.Y. Chan P.W. Lui W.F. Poon F.K. Lam H. Wang Department of Electrical & Electronic Engineering University of Hong Kong Hong Kong China Department of Anesthesiology Veterans General Hospital-Taipei Taipei Taiwan Department of Physiology National Cheng Kung University Tainan Taiwan

A fast detection algorithm for venous air embolism (VAE) was developed and implemented as a real-time monitor for detecting embolic heart sound and estimating embolic air volume. Its performance was evaluated under bolus injection of sub-clinical (0.0l to 0.80 ml) and continuous infusion of clinically significant (0.80 to 9.60 ml) air volumes in anaesthetized dogs. The clinically significant air emboli could be estimated based on the calibration curve obtained during sub-clinical VAE for a subject. The monitor also kept track of the cumulative embolic air volumes and alerted the anaesthetists once a predefined clinically significant embolic air volume was reached. As both humans and dogs share similar physiological conditions, our monitor for dogs are expected to be applicable to humans.

关键词： Wavelet analysis Heart Artificial intelligence Signal analysis Dogs Detection algorithms Calibration Humans Patient monitoring Algorithm design and analysis

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