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Comparison of learning algorithms for feedforward neural nets

Comparison of learning algorithms for feedforward neural net...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： J.A. Nossek P. Nachbar A.J. Schuler Institute for Network Theory and Circuit Design Technical University Munich Germany Technische Universitat Munchen Munchen Bayern DE

Several well known learning algorithms for feedforward two-layer neural nets and an improved version of Madaline I have been investigated and compared with respect to learning effort and classification capacity. These results, based on random training patterns, and their significance for generalization have been verified with real life data for ICR/OCR.

关键词： Neural networks Feedforward neural networks Backpropagation algorithms Data mining Training data Capacity planning Circuit synthesis electronic mail Optical character recognition software Supervised learning

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Hybrid-control of synapse circuits for programmable cellular neural networks

Hybrid-control of synapse circuits for programmable cellular...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： S. Espejo R. Dominguez-Castro R. Carmona A. Rodriguez-Vazquez Centro Nacional de Microelectrónica Universidad de Sevilla Edificio CICA Seville Spain Universidad de Sevilla Sevilla AndalucÃa ES

This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), based on auto-tuning of analog control signals to digitally specified values. The approach merges the advantages of digital and analog programmability, achieving low areas and reduced number of control lines, simplifying the control and storage of weight values, and eliminating their dependency on global process-parameter variations.

关键词： circuits Cellular neural networks electronic mail Very large scale integration Digital control Computer applications design optimization Signal processing Joining processes Voltage

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A new high-frequency very low output-impedance CMOS buffer

A new high-frequency very low output-impedance CMOS buffer

引用

ieee International symposium on circuits and systems (ISCAS)

作者： K. Manetakis C. Toumazou Department of Electrical and Electronic Engineering Imperial College of Science Technology and Medicine London UK

A technique to increase the transconductance of the MOS transistor by employing current feedback is presented and applied to the design of a voltage follower. Simulation results show that the output impedance of the buffer is kept very low over a wide range of frequencies while the input impedance remains very high. At the same time this buffer configuration shows wide bandwidth of operation, ability to drive large capacitive loads without oscillation and with very good linearity. Finally an example of a CFOA (current feedback op amp) using this buffer is presented.

关键词： Transconductance Impedance MOSFETs Voltage Mirrors CMOS technology Output feedback Bipolar transistor circuits Bipolar transistors Operational amplifiers

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design of pyroelectric IR readout circuit based on LiTaO/sub 3/ detectors

Design of pyroelectric IR readout circuit based on LiTaO/sub...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Wen-Yaw Chung Tai-Ping Sun Yung-Lung Chin Yuan-Liang Kao Institute of Electronic Engineering Chung Yuan Christian University Chungli Taiwan Chung-Shan Institute of Science and Technology CSIST Taoyuan Taiwan

This paper presents a design approach of pyroelectric readout circuit based on LiTaO/sub 3/ material for thermal imaging applications. To simulate the integrated effects of the pyroelectric detector and the sense amplifier readout circuit, the macro models of LiTaO/sub 3/-based pyroelectric detectors have been developed and verified by using the HSPICE simulator. Both computer simulation and hybrid-mode hardware realization of the pyroelectric readout circuit cell have been investigated in regard to voltage responsivity, noise analysis and specific detectivity. Good agreement has been found between computer simulation and measured performance on the voltage responsivity and noise effect.

关键词： Pyroelectricity Computational modeling Detectors Computer simulation Voltage Circuit noise Optical imaging Application software Circuit simulation Hardware

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Rate-constrained adaptive quantization scheme for wavelet pyramid image coding

Rate-constrained adaptive quantization scheme for wavelet py...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： J.Q. Ni K.L. Ho K.W. Tse Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong China

It is well known that orthogonal wavelet transform with filters of nonlinear phase gives poor visual results in low bit rate image coding. Biorthogonal wavelet is a good substitute, which is, however essentially nonorthogonal. A greedy steepest descend algorithm is proposed to design an adaptive quantization scheme based on the actual statistics of the input image. Since the L/sup 2/ norm of the quantization error is not preserved through the nonorthogonal transform, a quantization error estimation formula considering the characteristic value of the reconstruction filters is derived to incorporate the adaptive quantization scheme. Computer simulation results demonstrate significant SNR gains over standard coding technique, and comparable visual improvements.

关键词： Quantization Wavelet transforms Bit rate Image coding Algorithm design and analysis Statistics Estimation error Image reconstruction Adaptive filters Computer simulation

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A low power logarithmic A/D converter

A low power logarithmic A/D converter

引用

ieee International symposium on circuits and systems (ISCAS)

作者： F. Francesconi F. Maloberti Department of Electronics University of Pavia Pavia Italy

The architecture of a new logarithmic analog-to-digital converter employing a successive approximation algorithm is presented. We used a mixed capacitor-array, resistor-string structure for the logarithmic conversion. The converter was derived from its linear counterpart by modifying of the conversion algorithm. Computer simulations show that the proposed approach is suitable to design high quality audio converters in low power low voltage applications. A prototype of the converter has been implemented in a 1.6 /spl mu/m single poly double metal CMOS technology.

关键词： Dynamic range electronic mail Signal processing algorithms Computer simulation Low voltage CMOS technology Energy consumption Digital signal processing Signal to noise ratio Computer architecture

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A reconfigurable parallel inference processor for high speed fuzzy systems

A reconfigurable parallel inference processor for high speed...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M.J. Lees D.A. Campbell J.C. Devlin School of Electronic Engineering La Trobe University Australia

An application specific parallel rule inference architecture is presented which is capable of performing an entire rule inference within one clock cycle. The architecture is composed of asynchronous self routing min and max blocks that are interlinked into a network as determined by the rules for the intended application. The inference processor does not have to fetch rules from memory because the rules are configured in the firmware structure; hence the inherent speed advantage. The design is targeted for high capacity Complex Programmable Logic Devices (CPLDs), whose ability to be reconfigured allows the application specific rule structure to be practical for real world systems.

关键词： Fuzzy systems Pins Routing Programmable logic devices Fuzzy logic Hardware Computer architecture Clocks Microprogramming Inference algorithms

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Minimization of adders in fast FIR digital filters and its application to filter design

Minimization of adders in fast FIR digital filters and its a...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M. Yagyu A. Nishihara N. Fujii Department of Pliysical Electronics Tokyo Institute of Technology Japan

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. An algorithm is given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using MILP. Utilization of common expressions in Hartley's technique widen the CSD coefficient space. Thus the mixed integer linear programming (MILP) may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

关键词： Finite impulse response filter Digital filters Adders Frequency response electronic mail Logic design methodology Mixed integer linear programming Hardware Costs

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A pipelined VLSI with module structure design for discrete wavelet transforms

A pipelined VLSI with module structure design for discrete w...

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ieee International symposium on circuits and systems (ISCAS)

作者： Ming-Hwa Sheu Shun-Fa Cheng Ming-Der Shieh Department of Electronic Engineering National Yunlin Institute of Technology Yunlin Taiwan

This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform (DWT). The features of the architecture are (1) lower hardware cost, (2) shorter latency, (3) simplex control, (4) regular structure for VLSI implementation and (5) higher output throughput rate. Considering the precision of the transformed data, an accuracy analysis of the architecture has been carried out to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.

关键词： Discrete wavelet transforms Very large scale integration Computer architecture Hardware Filter bank Low pass filters Delay Application software Wavelet analysis Wavelet transforms

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FPGA based systolic array architectures for computing the discrete Fourier transform

FPGA based systolic array architectures for computing the di...

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ieee International symposium on circuits and systems (ISCAS)

作者： C.H. Dick School of Electronic Engineering La Trobe University Melbourne VIC Australia

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using custom computing machines based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that gives the system designer a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution times are calculated.

关键词： Field programmable gate arrays Systolic arrays Computer architecture Discrete Fourier transforms Programmable logic arrays Reconfigurable logic Logic arrays Arithmetic Logic circuits Digital signal processing

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