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design of low-power and low-voltage log-domain filters

Design of low-power and low-voltage log-domain filters

引用

ieee International symposium on circuits and systems (ISCAS)

作者： F. Yang C. Enz G. van Ruymbeke Electronics Laboratory LEG Swiss Federal Institute of Technology Lausanne Switzerland

This paper describes a component-level mapping between linear- and log-domain filters. A modified multiple input class AB log-integrator with both f- and Q-tuning is presented. A 3/sup rd/-order elliptic filter derived from a LC ladder prototype is designed using the proposed log building blocks and including the log-domain implementation of the transmission zero. Simulated frequency responses, THD and SNR, obtained from large signal transient analysis, are given. The filter is designed for a 2 V supply and consumes 1.3 mW for a cutoff frequency of 10 MHz. It can easily be frequency tuned from 1 MHz to 30 MHz.

关键词： Voltage Filters Energy consumption Frequency Dynamic range circuits Laboratories electronic mail Prototypes Filtering theory

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Benefits of vertically stacked integrated circuits for sequential logic

Benefits of vertically stacked integrated circuits for seque...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M. Reber R. Tielert Institute for Microelectronics University of Kaiserslautern Kaiserslautern Germany

Future demands for performance of electronic systems will push the development of three-dimensional (3-D) packaging technologies. Up to now 3-D stacking techniques are just used to realize high density memory modules. In this paper we investigate problems and solutions of sequential logic circuit design for vertically stacked integrated circuits (VIC). We analyze a test strategy and a 3-D placement tool for VICs that allows us to generate globally optimized circuit layouts by a 3-D arrangement of gates. Our focus is on test overhead obtained by the proposed test strategy for VICs and the reduction of wiring space attained by 3-D routing. Additionally we discuss the effect of our 3-D placement procedure on fault coverage. The results obtained using this procedure in different circuit layouts for 3-D circuits are compared to single chip solutions.

关键词： Sequential circuits Registers Testing Hardware Observability Controllability Semiconductor device measurement Wiring Feedback loop Multiplexing

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Physical MOSFET's model for analog circuit design: application to current copier based architectures

Physical MOSFET's model for analog circuit design: applicati...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： E. Robilliart E. Dubois IEMND/SEN UMR CNRS 9929 Villeneuve d'Ascq France

A one-dimensional numerical MOSFET model suitable for fast transient analysis of analog as well as digital circuits is presented. This model, based on a fast resolution of the Poisson and current continuity equations is continuous over all region of operation, from weak to strong inversion. Moreover, this modeling approach implicitly takes into account the non-quasi-static nature of the charge dynamics. This last feature proved to be very useful for the simulation of current copier based circuits that are strongly affected by charge injection effects. Systematic comparisons are given between this model, BSIM3 and two-dimensional (2D) simulations for basic and cascoded current copier cells.

关键词： MOSFET circuits Analog circuits Charge carrier processes Numerical models Circuit simulation electronic mail Transient analysis Digital circuits Analog-digital conversion Ear

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A high-performance distributed arithmetic processor for the HD video compression

A high-performance distributed arithmetic processor for the ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Hyoung-Gon Kim Je-Ho Lee Yong-Moo Kwon Division of Electronic and Information Tech KIST Seoul South Korea

This paper presents a design of high-performance Distributed Arithmetic Processor (DAP) for the efficient implementation of HD video compression algorithms. A Multi-Bit Pipelined Carry-Save DAP (MPCS-DAP) structure have been proposed where two pipelined carry-save accumulators implement the divided look-up table (LUT) DA structure with multi-bit processing in parallel. This structure enables flexible high speed operations at low power consumption based on the pipelined bit-sequential operations. A novel two-bit adder circuitry has been used extensively and HSPICE simulation of the critical path shows that it operates at 200 MHz clock speed at 3.3 volts with 0.8 /spl mu/m double metal CMOS technology. It has also shown that an array of MPCS-DAP can implements 2D DCT/IDCT at 200 M samples per second.

关键词： Arithmetic High definition video Digital audio players Table lookup CMOS technology Algorithm design and analysis Compression algorithms Energy consumption Adders circuits

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40 Gb/s, 3 volt InP HBT ICs for a fiber optic demonstrator system

40 Gb/s, 3 volt InP HBT ICs for a fiber optic demonstrator s...

引用

Annual ieee symposium on Gallium Arsenide Integrated Circuit (GaAs IC)

作者： T. Swahn T. Lewin M. Mokhtari H. Tenhunen R. Walden W.E. Stanchina Microwave and High Speed Electronics Research Center Erickson Microwave Systems Molndal Sweden Department of Electronics Electronic Systems Design Laboratories Royal Institute of Technology Kista Sweden Hughes Research Laboratories HRL Microwave Devices and Circuits Laboratory Malibu CA USA

We have designed and fabricated an InP HBT chip set intended for a 40 Gb/s fiber optic demonstrator system. The chip set consists of 14 different digital- and analog-ICs, and the project is a joint-venture between Ericsson Microwave systems AB and Hughes Research Laboratories. The project goal is to demonstrate 40 Gb/s fiber optical operation, to learn how to design very high speed/high frequency integrated circuits, and to expand our knowledge on circuit behaviour prediction.

关键词： Indium phosphide Heterojunction bipolar transistors Optical fibers Optical design High speed optical techniques Integrated optics Frequency Photonic integrated circuits Very high speed integrated circuits High speed integrated circuits

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The generalized CMAC

The generalized CMAC

引用

ieee International symposium on circuits and systems (ISCAS)

作者： F.J. Gonzalez-Serrano A. Artes-Rodriguez A. Figueiras-Vidal DTC-ETSI Telecomunicación Universidad de Vigo Vigo Spain DSSR-ETSI Telecomunicación UPM Madrid Spain

The cerebellar model arithmetic controller (CMAC) is a neurological model for human-like nonlinear controller design. The CMAC can approximate a wide variety of nonlinear functions by local training. The conventional CMAC uses receptive fields with equal width along all dimensions of input space without considering the variation of the target function in different areas. To avoid this limitation, we propose to adapt the width of the receptive fields depending an the input data distribution. The present paper describes this strategy and explores the application of the proposed algorithm in a nonlinear digital communications framework.

关键词： Hypercubes Telecommunication standards Telecommunication control Communication system control Neural networks electronic mail Arithmetic Digital communication Neurons Predictive models

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Noise properties of CMOS current conveyors

Noise properties of CMOS current conveyors

引用

ieee International symposium on circuits and systems (ISCAS)

作者： E. Bruun Department of Information Technology Technical University of Denmark Lyngby Denmark

The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current.

关键词： Voltage Semiconductor device modeling Noise reduction Performance analysis Signal processing Information technology electronic mail Operational amplifiers Mirrors Noise generators

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A unified algorithm for blind separation of independent sources

A unified algorithm for blind separation of independent sour...

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ieee International symposium on circuits and systems (ISCAS)

作者： Je Zhu Xi-Ren Cao M.L. Liou Department of Electrical & Electronic Engineering Hong Kong University of Science and Technology Kowloon Hong Kong China

This paper presents a unified algorithm of blind source separation based on the "Independent Component Analysis"(ICA) principle. The algorithm can separate all sources provided there is at most one Gaussian distributed source. The key point is to find a matrix by which the estimates of the original signals are pairwise independent in the absence of noises. If the observed signals are corrupted by noises, minimum-variance unbiased estimates are obtained. In comparison with the algorithm proposed previously by the authors, this algorithm has a parallel pipeline structure, and will not need a preset threshold if both of the 3rd- and 4th-order cumulants of any non-Gaussian distributed source are not zero. This algorithm has significant advantages over existing algorithms.

关键词： Blind source separation Signal processing algorithms Independent component analysis Vectors Matrix decomposition Water resources Algorithm design and analysis Sensor phenomena and characterization Noise cancellation Image enhancement

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Analysis of algorithms for nonuniform-time discrete Fourier transform

Analysis of algorithms for nonuniform-time discrete Fourier ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： D.M. Bland T.I. Laakso A. Tarczynski School of Electronic and Manufacturing Systems Engineering University of Westminster London UK University of Westminster London London GB Sch. of Electron. & Manuf. Syst. Eng. Univ. of Westminster London UK

In order to perform spectral analysis of nonuniformly sampled time domain signals, algorithms for the Nonuniform-Time Discrete Fourier Transform (NUT-DFT) are developed and evaluated The NUT-DFT takes nonuniform time domain data and produces a uniform sampled spectrum. The proposed algorithms for NUT-DFT are based on approximating the continuous-time Fourier transform by different numerical integration algorithms. Special attention is paid to the ability of the transform to capture signals with frequency components above half the average sampling rate. The performance of the algorithms is studied experimentally by analysing both nonuniformly and uniformly sampled data.

关键词： Algorithm design and analysis Time domain analysis Performance evaluation Spectral analysis Discrete Fourier transforms Fourier transforms Discrete transforms Frequency Sampling methods Performance analysis

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What is the state of the art in commercial EDA tools for low power? 96

What is the state of the art in commercial EDA tools for low...

引用

International symposium on Low Power electronics and design (ISLPED)

作者： O. Coudert R. Haddad K. Keutzer Synopsys Inc. Mountain View CA USA

ISBN: (纸本)9780780335714

Integrated circuit design has principally focused on achieving performance goals (e.g., speed) with minimal cost (e.g., area) using as little design time as possible. To help designers achieve these goals computer-aided design tools have traditionally focused on tools which improve performance, reduce area, and improve productivity. In the beginning of this decade, a new design concern began to surface. Motivated by the desire to differentiate products by longer battery life, designers of integrated circuits for portable products began to be worried about the power consumption of their electronics. Moreover, as the decade progressed and smaller processing geometries appeared on the horizon, the problem of packing millions of transistors into a cost-effective plastic package emerged. Finally, product reliability added a third motivation to address the issue of power dissipation. As we approach the end of the decade, it appears that power dissipation will eclipse area as a design concern for many integrated circuits. In response to this, the electronic-design automation industry is beginning to produce products which aid in the reduction of power dissipation of integrated circuits. This paper aims to review the state-of-the-art of commercial tools for reducing power dissipation.

关键词： electronic design automation and methodology Power dissipation Integrated circuit synthesis Costs design automation Productivity Batteries Energy consumption Computational geometry Plastics

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