A timing driven placement approach for very large circuits is described. A new method for accurate net delay estimation allows to calculate an individual delay between the source pin and each sink pin of a net. The ob...
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A timing driven placement approach for very large circuits is described. A new method for accurate net delay estimation allows to calculate an individual delay between the source pin and each sink pin of a net. The obtained timing information drives an efficient net-based placement technique, which dynamically adapts the net weights during successive placement steps. For the first time, results of benchmark circuits with up to 25,000 cells are presented. They show an excellent quality in terms of maximum path delay and total area after final routing. The maximum path delay of the examined circuits is reduced by 26% on an average, at an area cost of only 1% compared to the timing driven placement tool RITUAL 3.4.
This paper proposes an algorithm for the iterative design of FIR digital filters whose coefficients have minimum weight representation. The total number of nonzero bits is limited. In each iteration the coefficient ve...
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This paper proposes an algorithm for the iterative design of FIR digital filters whose coefficients have minimum weight representation. The total number of nonzero bits is limited. In each iteration the coefficient vector is up-dated so that some sets of the amplitude ripples become smaller. The direction is found by solving linear simultaneous equations. The method evaluates the normalized peak ripples in the minimax sense. Several examples show that the proposed method yields superior filter responses compared to the conventional methods.
The problems associated with applying the discrete cosine transform (DCT) to the design and implementation of the 1-D isotropic quadratic filter are investigated in this paper. A DCT implementation of the filter is pr...
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The problems associated with applying the discrete cosine transform (DCT) to the design and implementation of the 1-D isotropic quadratic filter are investigated in this paper. A DCT implementation of the filter is proposed and its computational complexity is analysed. The advantage of the DCT implementation is illustrated by a nonlinear system modelling problem. Results show that the DCT implementation converges faster than the direct implementation.
An adaptive electromagnetic optimization procedure to facilitate field-theoretic design of hybrid and monolithic integrated circuits is presented. This approach provides full-wave characterization of complex MIC and M...
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An adaptive electromagnetic optimization procedure to facilitate field-theoretic design of hybrid and monolithic integrated circuits is presented. This approach provides full-wave characterization of complex MIC and MMIC geometries by including various effects such as coupling, spurious radiation, surface wave modes, and interactions with package modes. Application of this procedure utilizing commercially available electromagnetic simulators is presented to demonstrate its versatility.< >
This paper describes an architecture based on a new full search block-matching algorithm called vector-characterization algorithm (VCA). A single-chip realization in form of a 1.0 /spl mu/m CMOS standard cell design s...
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This paper describes an architecture based on a new full search block-matching algorithm called vector-characterization algorithm (VCA). A single-chip realization in form of a 1.0 /spl mu/m CMOS standard cell design shows that the architecture is suitable for HDTV applications.
Nowadays, the addition of specific hardware to CAD or DA applications has been received by the engineering community. Specially, Content Addressable Memory (CAM) is in the limelight because of its fast processing capa...
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Nowadays, the addition of specific hardware to CAD or DA applications has been received by the engineering community. Specially, Content Addressable Memory (CAM) is in the limelight because of its fast processing capability. In this paper, we propose a new algorithm and reformed CAM to deal with the sorting problem that always takes the bulk of the execution time in some applications such as design-rule checking. They can effect an 80% reduction in retrieval times.
Regulatory standards such as IEC555-2 require switch-mode power supplies (SMPS) to have a high power factor. The addition of a power-factor-correction (PFC) pre-regulator to an SMPS may enable it to meet the regulator...
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Regulatory standards such as IEC555-2 require switch-mode power supplies (SMPS) to have a high power factor. The addition of a power-factor-correction (PFC) pre-regulator to an SMPS may enable it to meet the regulatory requirement. But this is, in most cases, not an optimum design. Based on the example of a power supply system for telecommunication applications, a method to optimize the overall design is presented in this paper. In the new design the need for a separate SMPS (in addition to the PFC pre-regulator) is eliminated. Computer simulations are presented to show that the new design approach is possible and practical.
This paper discusses the design of a neural network for solving some classes of combinatorial optimization problems in real time. By means of a suitable design procedure which is not based on energy arguments, it is g...
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This paper discusses the design of a neural network for solving some classes of combinatorial optimization problems in real time. By means of a suitable design procedure which is not based on energy arguments, it is guaranteed that the network is devoid of spurious responses. An important application is considered to a typical optimization problem arising in the telecommunications field. More specifically, we show how the neural network can be used to take decisions for switching packets and improve switching performance in a fast packet switching fabric with input buffers.
Recent availability of the public-domain EKV (Enz-Krummenacher-Vittoz) MOST model from EPFL in a number of circuit simulators facilitates the intuitive design, analysis and simulation of analogue and mixed-mode circui...
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Recent availability of the public-domain EKV (Enz-Krummenacher-Vittoz) MOST model from EPFL in a number of circuit simulators facilitates the intuitive design, analysis and simulation of analogue and mixed-mode circuits and systems exploring the numerous modes of operation of the MOST, particularly at low-voltage (LV) and low-current (LC). A practical approach for either extracting the most critical parameters and/or adapting those already available from widely used SPICE models (levels 2 and 3) for use with the EKV model is presented and opportunities for engineering education are considered. The effectiveness of the approach is illustrated by measured results from CMOS and BiCMOS technologies.
A discrete-time dynamic model of closed-loop switched mode electronic regulators is derived. No small-ripple approximations are required. The same model serves for both local and global stability study: by discarding ...
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A discrete-time dynamic model of closed-loop switched mode electronic regulators is derived. No small-ripple approximations are required. The same model serves for both local and global stability study: by discarding the nonlinear terms (like products of small-signal perturbations in the converter state variables) and using the z-transform, a local stability criteria is formulated. Applying the condition that the eigenvalues of the z-domain characteristic matrix have to be situated inside the unit circle, a design constraint on the feedback gains is found. An example of a boost converter operating in continuous conduction mode with inductor current and output voltage feedback is presented.
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