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A family of low cost high performance HEMT MMICs for commercial DBS applications

A family of low cost high performance HEMT MMICs for commerc...

引用

ieee symposium on Microwave and Millimeter-Wave Monolithic circuits

作者： K. Hubbard K. MacGowan C. Kau D. Smith S. Maas Space and Electronics Group Electronic Systems and Technology Division TRW CA USA

A family of GaAs HEMT MMICs have been developed for use in Direct Broadcast Satellite TV (DBS) US, Japanese, and European markets. These designs are very compact, high performance, and self-biased. They are meant as building blocks for low noise block (LNB) downconverters. Described in this paper are the receiver chip, low noise amplifier, and self-biased single HEMT device (should a MIC LNA be preferred). The key design is the receiver chip with a nominal gain of 38 dB and NF of less than 3 dB for the US band. This paper presents a description of each design, a performance summary, as well as information describing their actual use in an LNB design.< >

关键词： Costs HEMTs MMICs Satellite broadcasting Gallium arsenide TV Low-noise amplifiers Microwave integrated circuits Gain Noise measurement

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Generation of multi-polarity arithmetic transform from reduced representation of Boolean functions

Generation of multi-polarity arithmetic transform from reduc...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： B.J. Falkowski Chip-Hong Chang School of Electrical and Electronic Engineering Nanyang Technological University Singapore

A new algorithm is given that converts a reduced representation of Boolean functions in the form of disjoint cubes to multi-polarity arithmetic spectrum. Since the known algorithms that generate arithmetic spectrum always start from the truth table of Boolean functions the method presented computes faster with a smaller required memory. The algorithm is extremely efficient for such Boolean functions that are described by only few disjoint cubes and it allows the calculation of only selected spectral coefficients, of all the coefficients which can be calculated in parallel.

关键词： Arithmetic Boolean functions Polynomials Testing Stochastic processes Image analysis Minimization Image coding Cryptography Algorithm design and analysis

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An architecture for integrated reliability simulators using analog hardware description languages

An architecture for integrated reliability simulators using ...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： S.M. GadelRab J.A. Barby S.G. Chamberlain Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada

A new architecture for integrated reliability simulators is presented. The architecture is compatible with analog hardware description language simulation environments. Simulator integration is achieved by incorporating the reliability evaluation routines into the component templates through the use of analog states. An internal simulation control mechanism is substituted for the external control shell found in conventional reliability simulators. The architecture supports iterative and multi-step reliability simulation schemes. A prototype reliability simulator for amorphous silicon circuits is also presented.

关键词： Hardware design languages Circuit simulation Degradation Stress Integrated circuit reliability Convergence Computational modeling Virtual prototyping Amorphous silicon electronic mail

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design methodology for low power data compressors based on a window detector in a 54/spl times/54 bit multiplier

Design methodology for low power data compressors based on a...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M. Song K. Asada Semiconductor Design Center Samsung Electronics Japan Company Limited Japan Department of Electronic Engineering University of Tokyo Japan

Currently, a typical 54/spl times/54 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is a design methodology for the low power data compressors based on an intelligent window detector. The role of the window detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a window) is activated. Therefore, it can be called an intelligent window detector. Using it, the average power consumption of the proposed data compressors is reduced by about 35%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one.

关键词： design methodology Compressors Energy consumption Data compression Gas detectors Propagation delay Very large scale integration Algorithm design and analysis Data engineering design engineering

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CAD in test

CAD in test

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ieee International symposium on Industrial electronics (ISIE)

作者： T. Riesgo E. de la Torre Y. Torroja E. Olias J. Uceda División de Ingeniería Electrhical Universidnd Politécnica de Madrid Madrid Spain Escuela Politécnica Superior Área de Tecnología Electrónical Universidad Carlos III de Madrid Madrid Spain

This paper presents a survey of the most important computer aided design (CAD) tools used for testing purposes. The paper is oriented to give an overview of the main techniques used in test, as well as an advance of the technology that is foreseen in the test arena for the future. The most advanced test methods have been typically developed for integrated circuits. As digital systems grow in complexity, some of the techniques used in IC testing are being used for systems. For this reason, this paper mainly deals with CAD tools for IC testing, although some extensions are presented, for system testing.

关键词： Circuit testing System testing Integrated circuit testing design for testability design automation design methodology electronic equipment testing Integrated circuit technology Paper technology Digital systems

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A novel algorithm for multi-operand logarithmic number system addition and subtraction using polynomial approximation

A novel algorithm for multi-operand logarithmic number syste...

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ieee International symposium on circuits and systems (ISCAS)

作者： I. Orginos V. Paliouras T. Stouraitis VLSI Design Laboraotory Electrical Engineering Dept University of Patras Greece

In this paper, a novel algorithm for multi-operand Logarithmic Number System (LNS) addition and subtraction is presented. In particular, the computation of the nonlinear functions required for logarithmic addition and subtraction is decomposed into computing 2/sup -x/, log/sub 2/(1+x), some additions, and some shifts. The error behaviour of the algorithm is analyzed, upper bounds of the computational error are provided and it is shown that the introduced Propagation Error Cancellation (PEG) technique and the Error Spectrum Shaping can significantly narrow the error distribution. The inherent parallelism of the proposed algorithm and the pipelinability that exists in the computation of 2/sup -x/ and log/sub 2/(1+x) by using polynomials are exploited by simple VLSI architectures that exhibit important speed-up over the equivalent ROM-based designs. Also, a rule for the determination of the optimal number of pipeline stages is suggested.

关键词： Polynomials Very large scale integration Computer architecture Chebyshev approximation electronic switching systems Approximation algorithms Algorithm design and analysis Read only memory Upper bound Distributed computing

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Dynamic range of low-voltage cascode current mirrors

Dynamic range of low-voltage cascode current mirrors

引用

ieee International symposium on circuits and systems (ISCAS)

作者： E. Bruun P. Shah Electronics Institute Technical University of Denmark Lyngby Denmark Department of Electrical and Electronic Engineering Imperial College London London UK

Low-voltage cascode current mirrors are reviewed with respect to the design limitations imposed if all transistors in the mirror are required to operate in the saturation region. It is found that both a lower limit and an upper limit exist for the cascode transistor bias voltage. Further, the use of a signal dependent cascode bias voltage is discussed and a self-biased cascode configuration is presented. This configuration makes it possible to use a higher effective gate-source voltage for the mirror transistors, hence reducing the effect of threshold voltage mismatch on the current mirror gain. The proposed configuration has the advantage of simplicity combined with a complete elimination of the need for fixed bias voltages or bias currents in the current mirror. A disadvantage is that it requires a higher input voltage to the current mirror.

关键词： Dynamic range Mirrors Threshold voltage Low voltage Equations Transistors Analog circuits Educational institutions Impedance Transconductance

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design concepts for the reactor protection and control process instrumentation digital upgrade project at the Donald C. Cook nuclear plant units 1 and 2

Design concepts for the reactor protection and control proce...

引用

ieee symposium on Nuclear Science (NSS/MIC)

作者： R.C. Carruth S.G. Sotos Nuclear I&C Design American Electric Power Service Corporation Columbus OH USA American Electric Power Service Corporation Columbus OH USA

As the nation's nuclear power plants age, the need to consider upgrading of their electronic protection and control systems becomes more urgent. Hardware obsolescence and mechanical wear out resulting from frequent calibration and surveillance play a major role in defining their useful life. At Cook Nuclear plant, a decision was made to replace a major portion of the plant's protection and control systems with newer technology. This paper describes the engineering processes involved in this successful upgrade and explains the basis for many decisions made while performing the digital upgrade.

关键词： Inductors Protection Digital control Process control Instruments Control systems Automatic control Communication system control Nuclear electronics Solid state circuits

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Efficient variable rate vector quantization using quadtree segmentation

Efficient variable rate vector quantization using quadtree s...

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ieee International symposium on circuits and systems (ISCAS)

作者： Hung Yuen Kam-Chi Li L. Hanzo Department of Electronic Engineering Hong Kong Polytechnic Institute Hong Kong China Department of Electronics and Computer Science University of Southampton UK

Variable rate vector quantization (VQ) using greedy tree growing algorithm has been used in image compression. In previous work, images have been partitioned into fined size blocks and therefore correlation existing in large variable size blocks cannot be exploited. In this paper, a new and efficient variable rate vector quantization scheme using variable block sizes is introduced. Simulation results show that the proposed scheme which is based on variable block size quadtree segmentation can achieve better performance than the fixed block size variable rate VQ.

关键词： Vector quantization Image segmentation Image coding Data compression Algorithm design and analysis Rate distortion theory Computer science Shape Encoding Testing

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Optimization of VLSI allocation

Optimization of VLSI allocation

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Zhongli He Dian Zhou Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Hong Kong China

Allocation is one of main tasks in the high level synthesis. It includes module selection, functional unit allocation, storage allocation and interconnection allocation. In this paper, we model the allocation problem as cluster analysis and apply a new algorithm, neighbor state transition (NST) algorithm, for cluster optimization. It is proved that the algorithm produces an asymptotically global optimal solution with the upper bound on the cost function (1+0(1/n)/sup 2-/spl epsiv//)F*, where F* is the cost of the optimum solution, n is the problem size and /spl epsiv/ is a positive parameter arbitrarily close to zero. The numerical examples show that the NST algorithm produces better results compared to the other known methods.

关键词： Very large scale integration Clustering algorithms Cost function Algorithm design and analysis Upper bound Helium Optimization methods Hardware

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