An algorithm has been developed to calculate the arithmetic transform of Boolean functions from their Ordered Binary Decision Diagram (OBDD) representation. The method of decomposition of arithmetic spectral coefficie...
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An algorithm has been developed to calculate the arithmetic transform of Boolean functions from their Ordered Binary Decision Diagram (OBDD) representation. The method of decomposition of arithmetic spectral coefficients in terms of the cofactors of Boolean functions that resembles known Shannon decomposition of such functions has been introduced for the first time. Based on the above decomposition, a second new algorithm is presented to synthesize Ordered Binary Decision Diagrams directly from the arithmetic spectrum of Boolean functions.< >
A method is described which can be used to design two-dimensional nonrecursive linear-phase filters. The approach is based on formulating the absolute mean-square error between the amplitude responses of the practical...
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A method is described which can be used to design two-dimensional nonrecursive linear-phase filters. The approach is based on formulating the absolute mean-square error between the amplitude responses of the practical and ideal digital filters as a quadratic function. The coefficients of the filters are obtained by solving a set of linear equations. This method leads to a lower mean-square error and is computationally more efficient than the eigenfilter method. The method is extended to the design of filters with time-domain constraints.< >
The paper presents problems of applying synthesis techniques to FPGA-based design. The target architecture consists of a linear array of FPGAs in which to each FPGA there is a RAM attached to it. An attempt to utilise...
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The paper presents problems of applying synthesis techniques to FPGA-based design. The target architecture consists of a linear array of FPGAs in which to each FPGA there is a RAM attached to it. An attempt to utilise RAM is illustrated with random number generator as an example.< >
This paper reports on establishing a good starting point for a half-band fixed-point polyphase filter design technique, which employs a natural algorithm, when fifth and seventh order filter structures are used. It sh...
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This paper reports on establishing a good starting point for a half-band fixed-point polyphase filter design technique, which employs a natural algorithm, when fifth and seventh order filter structures are used. It should be noted that the convergence of combinatorial algorithms is sensitive to initial conditions implying that the seed filter coefficients and search space for subsequent filters need to be chosen with care for the algorithm to converge efficiently. This requires the definition of a bounded area and bounded volume in the coefficient space for the fifth and seventh order filters respectively. This will ensure that the zeroes are on the unit circle, and hence, will result in maximum null depths being achieved at the zero frequencies (as is the case with the elliptic approximation).< >
Integrated active inductor configurations for RF frequencies are examined in this paper. A new aspect of comparing the performance of different topologies is used, and consequent differences between technologies are r...
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Integrated active inductor configurations for RF frequencies are examined in this paper. A new aspect of comparing the performance of different topologies is used, and consequent differences between technologies are recognised. On the basis of these studies a new method for raising the Q-factor is presented and its applications considered.< >
The designed BiCMOS current-feedback operational amplifier utilizes a novel circuit topology which enables constant 1 MHz bandwidth closed loop voltage gains up to 60 dB. The offset current of the current-feedback amp...
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The designed BiCMOS current-feedback operational amplifier utilizes a novel circuit topology which enables constant 1 MHz bandwidth closed loop voltage gains up to 60 dB. The offset current of the current-feedback amplifier is canceled with an active OTA-C feedback loop. The amplifier is fabricated with a 1.2 micron BiCMOS-process (NPN f/sub T/ 7 GHz).< >
Three methods for the design of recursive allpass filters are presented. In one of these methods, a least-squares error based on the difference between the desired and actual frequency responses is formulated in a qua...
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Three methods for the design of recursive allpass filters are presented. In one of these methods, a least-squares error based on the difference between the desired and actual frequency responses is formulated in a quadratic form. In the other methods, a least-squares error based on the difference between the desired and actual phase responses is formulated in a quadratic form. In all the methods, the coefficients of the allpass filters are obtained by solving a system of linear equations. By appropriately choosing the weighting function we are able to design allpass filters that are optimal in the least-squares sense as well as the minimax sense. Examples are provided to demonstrate the efficacy of the methods.< >
This paper presents a design method of linear phase PR QMF banks of the second approach. H/sub 1/(z) can be optimized not only in L/sub 2/-norm sense, but also in L/sub /spl infin//-norm sense (essentially, in any sen...
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This paper presents a design method of linear phase PR QMF banks of the second approach. H/sub 1/(z) can be optimized not only in L/sub 2/-norm sense, but also in L/sub /spl infin//-norm sense (essentially, in any sense). Even in L/sub 2/-norm sense, the proposed method is more efficient than the Lagrange multiplier method. The proposed design method can be extended to M(>2)-channel systems immediately. Simulation results are shown for 2- and 3-channel systems, respectively.< >
This paper presents a design technique for high fidelity multistage decimation filters based on polyphase and decimator structures, catering for powers of two sample-rate decreases. The technique is well suited for An...
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This paper presents a design technique for high fidelity multistage decimation filters based on polyphase and decimator structures, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 15 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit flipping algorithm". This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to other approximation methods. The coefficients and frequency responses of the cascaded filter are reported.< >
This paper describes the design of a FFT chip, up to eight of which may be cascaded together to produce continuous streams of transforms of up to 65536 points. The control structure is asynchronous, and hence a fast, ...
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This paper describes the design of a FFT chip, up to eight of which may be cascaded together to produce continuous streams of transforms of up to 65536 points. The control structure is asynchronous, and hence a fast, very low power, slew-free environment is provided. Aspects of the event controlled methodology used for this, and other designs, is also presented.
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