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A fast array architecture for block matching algorithm

A fast array architecture for block matching algorithm

引用

ieee International symposium on circuits and systems (ISCAS)

作者： J. Baek Seunghyun Nam Moonkey Lee Chuldong Oh Kisoo Hwang Department Electronic Engineering Shichondong Seodaimoonku Yonsei University Seoul South Korea Hyundai Electronics Corporation South Korea

The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. Based on two dimensional systolic array, VLSI architecture for an implementation of full-search block matching algorithm is described. The proposed architecture has the following advantages: (1) it allows serial data inputs to save pin counts but performs parallel processing. (2) It is flexible in adaptation to the dimensional change of search window with simple control logic. (3) It has no idle time during the operation. (4) It can operate in real time for videoconference application and EDTV application. (5) It is modular and regular in design, and thus suitable for VLSI implementation.< >

关键词： Very large scale integration Strontium Motion estimation Shift registers Switches Image coding Image sequences Systolic arrays Parallel processing Logic design

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Intelligent enhancements for conventional layout systems to support the design of printed circuit boards

Intelligent enhancements for conventional layout systems to ...

引用

ieee/CHMT(CPMT) International electronics Manufacturing Technology symposium

作者： K. Feldmann M. Koch A. Rothhaupt Institute for Manufacturing Automation and Production Systems University of Erlangen Germany

In designing printed circuit boards (PCBs) several important aspects need to be considered. First of all the desired functionality of the PCB has to be realized. This central task is supported by conventional PCB layout systems. Furthermore, the design process is influenced by two factors: the available manufacturing equipment; the estimated prime costs of production for the PCB. These two aspects have also to be drawn into consideration by the designer. Looking at conventional layout systems there is no support available for these tasks at the moment. The designer has to rely completely on his own experience and knowledge. This paper presents a Computer Aided design Environment (CADE), which enables the designer to gain information about the manufacturing restrictions and the estimated prime costs of production. Making use of the acquired information, he is able to review his design decisions and if necessary revise the layout.< >

关键词： Printed circuits Costs Computer aided manufacturing electronic equipment testing Circuit faults design engineering Circuit testing Production systems Electrical fault detection Fault detection

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A new efficient 2-D LMS adaptive filtering algorithm

A new efficient 2-D LMS adaptive filtering algorithm

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Sau-Gee Chen Yung-An Kao Department of Electronics Engineering National Chiao Tung University Hsinchu Taiwan

A new efficient 2-D LMS adaptive filtering algorithm is proposed in this work. The new algorithm costs N/sup 2//2-1 less multiplications, at the expense of N/sup 2//2 more additions than the existing 2-D direct-form LMS algorithms per adaptive iteration. Performance of the new algorithm is shown to be comparable to that of the known algorithms by theoretical analysis and simulation results, in the aspects of SNR and convergence rate. The new algorithm has N/sup 2/+1 coefficients, in contrast to N/sup 2/ coefficients of the conventional algorithms.< >

关键词： Least squares approximation Adaptive filters Filtering algorithms Costs Algorithm design and analysis Analytical models Adaptive algorithm Computational complexity electronic mail Convolution

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On absolute stability of neural networks

On absolute stability of neural networks

引用

ieee International symposium on circuits and systems (ISCAS)

作者： M. Forti A. Liberatore S. Manetti M. Marini Electronic Engineering Department University of Florence Florence Italy

The aim of this paper is to discuss the role of Absolute Stability (ABST) in the design of neural optimization solvers and to find necessary and sufficient conditions for ABST for some classes of neural networks of applicative interest. By ABST it is meant that there is a unique equilibrium point attracting all trajectories of motion and that this property is valid for all neuron activation functions belonging to a specified class of nonlinear mappings and for all constant neural network inputs. ABST neural networks are best suited for solving optimization problems being devoid of spurious suboptimal responses for every choice of the activation function and of the input vector. A necessary and sufficient condition for ABST has been found for symmetric neural networks of the Hopfield type. In this paper, we show that the concept of ABST can be applied also to special classes of nonsymmetric Hopfield neural networks and to neural models different from the Hopfield one. It is shown in particular that necessary and sufficient conditions for ABST can be found for two interesting classes of nonsymmetric networks, namely, cooperative Hopfield-type networks and composite neural networks with variable and constraint neurons used for solving linear and quadratic programming problems in real time.< >

关键词： Neural networks Neurons Sufficient conditions Hopfield neural networks Circuit stability Computer networks Symmetric matrices electronic mail design optimization Trajectory

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A distributed reconfiguration controller for linear array harvest problem: hierarchically quasi-normalized neural approach

A distributed reconfiguration controller for linear array ha...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： S. Sutikno M. Kaneko M. Onoda Dept. of Electr. & Electron. Eng. Tokyo Inst. of Technol. Japan Department of Electrical and Electronic Tokyo Institute of Technology Tokyo Japan

WSI is considered liable to have several faults at the beginning of the production stage and during its operating lifetime. This paper describes a design of distributed controller for reconfiguration on harvesting linear array system as a degradable system with assumption that not only basic cells but also the connection links are subject to fault condition. An inherently distributed feature of a new class of cellular neural network is used in hierarchical method. The proposed method is a simple heuristic distributed process with cellular (next neighbor) information. It has simple structures that have minimum penalty in WSI area thus minimizing the reliability cost.< >

关键词： Distributed control Neural networks Circuit faults Tail Multiplexing Neurons Decoding Production Control systems Degradation

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A new 2-D zero phase digital filter design with quadrantally symmetric or antisymmetric properties

A new 2-D zero phase digital filter design with quadrantally...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： J.Y. Chang W.H. Wang Control Engineering Department National Chiao Tung University Taiwan

A closed-form least-squares solution for the problem of designing two-dimensional (2-D) real zero phase Finite Impulse Response (FIR) filters with quadrantally symmetric or antisymmetric properties is obtained. Then a 2-D Infinite Impulse Response (IIR) filter is synthesized as an approximation of the designed 2-dimensional FIR filter by using the decomposition theorem and the 1-D balanced approximation (BA) method. The designed 2-D IIR filter retains good zero phase property over the passband region. The magnitude error between the 2-D FIR and the 2-D IIR filter is small and can be obtained from the BA method.< >

关键词： Digital filters Finite impulse response filter Matrix decomposition IIR filters Symmetric matrices Frequency response Passband Nonlinear filters electronic mail Two dimensional displays

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Integrated BiCMOS IF-modules for mobile telecommunication applications

Integrated BiCMOS IF-modules for mobile telecommunication ap...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： K. Halonen V. Porra P. Alinikula K. Koli H. Riihihuhta J. Hannikainen Electronic Circuit Design Laboratory Microelectronics Center Helsinki University of Technology Espoo Finland

Integrated IF-modules for mobile phone applications have been designed with-1.2 um BiCMOS technology. These modules consist of the transmitter, receiver and temperature independent gain-adjustment circuits. The 80 dB dynamic range over 50 MHz bandwidth of both the transmitter and receiver is achieved with the current stearing gain control amplifier. The gain control amplifier has an 80 dB dynamic range which is achieved with the current stearing gain control amplifier. The gain control is linear within +/- 0.5 dB and temperature compensated. The temperature compensation is performed in current mode. The dynamic range requirement is especially challenging for the logarithmic amplifier in the peak detector, in which a current feedback amplifier has been applied. These modules are intended to be combined on a single chip with the realised baseband filtering circuit. The total area of the circuits is 6 mm2 and the power consumption is 60 mA.< >

关键词： BiCMOS integrated circuits Gain control Dynamic range Transmitters Temperature Mobile handsets Integrated circuit technology Bandwidth Detectors Feedback amplifiers

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Intermediate signed-digit stage to perform residue to binary transformations based on CRT

Intermediate signed-digit stage to perform residue to binary...

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ieee International symposium on circuits and systems (ISCAS)

作者： F. Pourbigharaz H.M. Yassine Department of Electrical Engineering and Electronics Brunei University Uxbridge UK

A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. The conversion from residue to binary is performed in three levels: residue to signed-digit; signed-digit to binary; end-around carry adder/subtracter. By choosing the residue number systems based on (2/sup m/-1, 2/sup m/+1) or (2/sup m/-1, 2/sup m/+1, 2/sup 2m/+1) moduli sets, the necessary multiplication operations embedded within the CRT can be replaced by simple shift left operations. The CRT equation is realized by using redundant adder/subtracter blocks in the first level and the carry propagation is totally eliminated. The second level of operation converts the redundant form of CRT to the binary representation. The proposed architecture is free of modulo-M adders. This is achieved by using an end-around carry propagate adder/subtracter in the third level. The two moduli converter was designed and simulated on Cadence.< >

关键词： Cathode ray tubes Dynamic range Equations electronic mail Hardware Algorithm design and analysis Arithmetic Signal processing algorithms Digital signal processors Fault tolerant systems

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A hybrid analytical/intelligent approach to the modeling and control of DEDS

A hybrid analytical/intelligent approach to the modeling and...

引用

ieee International symposium on Computer Aided Control System design (CACSD)

作者： E.W. Kamen G. Vachtsevanos A. Doustmohammadi W. Mahmood School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

Many manufacturing processes, such as those arising in electronic circuit assembly and packaging, are characterized by both continuous variables and discrete event dynamics. The design of innovative end effective monitoring and control strategies for these processes requires the development of new models that can capture the hybrid continuous/discrete dynamic nature of the processes and can address the performance objectives in a systematic way. Although then, exists an extensive theory of modeling and control for continuous variable dynamic systems (CVDS), as of yet there is no comparable counterpart for the study of discrete event dynamic systems (DEDS), and there is no general systematic approach for combining CVDS and DEDS methodologies for the study of hybrid processes such as those arising in manufacturing systems. This paper introduces a new methodology for modelling, simulation and control of hybrid CVDS/DEDS processes with application to manufacturing systems. A key feature of the proposed approach is the use of a hierarchical modelling philosophy that capitalizes upon control theoretic concepts and tools from the area of fuzzy logic and neural networks.< >

关键词： Electric variables control Manufacturing processes Process control Manufacturing systems Minimax techniques Monitoring Job shop scheduling circuits Assembly Packaging

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A MMIC chip set for V-band crosslink communication systems

A MMIC chip set for V-band crosslink communication systems

引用

ieee symposium on Microwave and Millimeter-Wave Monolithic circuits

作者： K. Minot M. Aust R. Kasody R. Katz H. Wang P. Rodgers D. Smith L. Shaw K. Tan N. Wang S. Dow B. Allen Space & Defense Sector Electronic Systems & Technology Division TRW Redondo Beach CA USA Electron. & Technol. Div. TRW Inc. Redondo Beach CA USA

V-band communication crosslink systems are being developed to take advantage of high atmospheric-attenuation characteristics. Because of strict weight, volume, and cost constraints of modern satellites, MMIC technology was chosen over conventional MIC approaches to deliver lighter, smaller, and higher performance communication systems. Through the MIMIC Phase 2 program, sponsored by ARPA and the Army Research Laboratory, TRW has developed a chip set for such a crosslink. Requirements from several insertion programs have been integrated to design an architecture that is generic, but flexible enough for expansion or reconfiguration to support these programs. The chip set includes nine highly integrated, multi-function MMICs configured to provide a complete V-band transceiver system.< >

关键词： MMICs Frequency Noise figure Space technology Low-noise amplifiers HEMTs Gain measurement Semiconductor device measurement Feedback amplifiers Laboratories

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