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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?

Panel: Realistic low power design: Let errors occur and corr...

引用

ieee symposium on On-Line Testing (IOLTS)

作者： Abhijit Chatterjee Jacob Abraham Adit Singh Elie Maricau Rakesh Kumar Christos Papachristou Georgia Tech. USA University of Texas at Austin USA Auburn University USA KU Leuven Belgium University of Illinois at Urbana-Champaign USA Case Western Reserve University USA

There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that errors do not impact the Quality of Service of the end application or to allow errors to occur and correct them using error tolerance mechanisms. Specific signal processing algorithms have been shown to be inherently tolerant to errors. However, large general purpose processors experience virtually zero errors under supply voltage scaling up to a certain scaling level and then exhibit “massive errors” or “complete breakdown”. The problem is made worse by the fact that low power design methodologies force devices to be sized in such a way as to make a large number of circuit paths “critical”. Under all of the above constraints, what is the best way to build low power systems of the future using deeply scaled CMOS technologies? Is the use of voltage overscaling along with error resilience techniques realistic? Can we allow errors to occur and compensate for them with high confidence? Under what conditions will design guardbanding be absolutely necessary? If we do let errors occur periodically, will customers buy the associated products and is there a marketplace for such error-resilient ICs?

关键词： Error correction Process design Process control Resilience CMOS technology CMOS logic circuits Quality of service Signal processing algorithms Breakdown voltage design methodology

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Cost-performance driven mixed-signal system partitioning: a case study on SDH/SONET OAN interface

Cost-performance driven mixed-signal system partitioning: a ...

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International symposium on High Density Packaging and Microsystem Integration (HDP)

作者： Meigen Shen Li-Rong Zheng H. Tenhunen Laboratory of Electronics and Computer Systems IMIT Royal Institute of Technology Stockholm Sweden

For a complex electronic system, early estimation of what technology should be used is very important. In this paper, an optical network access interface is optimally designed according to cost-performance trade-off analysis. The results of the comparison show that for such a complex, mixed-signal system, single chip is not a cost-effective solution compared with single package which has 6 small chips.

关键词： Computer aided software engineering circuits Cost function Performance analysis Consumer electronics Optical fiber networks Optical design Packaging Ultraviolet sources CMOS technology

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A Memory-Efficient High-Speed Event-based Object Tracking System

A Memory-Efficient High-Speed Event-based Object Tracking Sy...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Yuncheng Lu Kaixiang Cui Yucen Shi Zehao Li Junying Li Wenhao Lu Yuanjin Zheng Tony Tae-Hyoung Kim School of Electrical and Electronic Engineering Nanyang Technological University

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Dynamic vision sensors (DVS) have become prevalent in edge vision applications due to their low power and short latency attributes. However, current DVS-based object tracking systems suffer from high power consumption or long processing latency due to high computing intensity of the object detection algorithms. This paper proposes an energy-efficient object detection system through algorithm and hardware co-optimization. We design hardware-efficient denoising and region proposal (RP) algorithms to reduce on-chip memory usage and power consumption. Besides, the processing latency is dramatically reduced thanks to the less computing complexity. The devised algorithm is executed on a heterogeneous platform, with segments particularly sensitive to latency being accelerated via FPGA. An RP processor, supporting both parallel and systolic computing modes, is developed to facilitate the computing-intensive RP generation. Remarkably, the proposed system reduces the on-chip memory by 95.3% in contrast to traditional methods that employ connected component labeling. Moreover, the processing time per frame stands at 92.2 ms, marking a reduction of 82.4% compared to CPU-only operations.

关键词： Power demand Heuristic algorithms Noise reduction Object detection Vision sensors System-on-chip Object tracking

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BEOL NEM Relay-Based Inductorless DC-DC Converters

BEOL NEM Relay-Based Inductorless DC-DC Converters

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Ren Li Dias Azhigulov Ahmed Allehyani Hossein Fariborzi Computer Electrical and Mathematical Sciences and Engineering Division King Abdullah University of Science and Technology Thuwal Saudi Arabia Electrical and Computer Engineering Department Nazarbayev University Nur-Sultan Kazakhstan Electrical and Electronic Engineering Department University of Jeddah Jeddah Saudi Arabia

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

In the past few years, Back-End-of-Line (BEOL) Nano-electromechanical (NEM) relays have emerged as promising switching devices for the beyond-CMOS era, due to their zero-leakage current property, and the compatibility to CMOS fabrication processes. Though the mechanical movement causes the relays to be inherently slower than transistors, the metallic contact interface untethers the limitation on gate-to-drain voltage, which makes the relays capable of handling higher voltages. In this work, we propose novel designs for BEOL NEM relay-based inductorless DC-DC converters for on-chip voltage conversions. The design, implementation, and analysis of buck (step-down) and boost (step-up) converters are shown. Both converters consist of only four NEM relays, respectively. By utilizing the charge pump topology in a switched-capacitor configuration, the relay converters exhibit lower output ripple and higher efficiency compared to their CMOS counterparts. This is particularly valuable for DC-DC voltage conversions in the Internet of Things chips, where the converter switching frequency is moderate, while the demands for efficiency, area saving, and on-chip integration are high.

关键词： Relays Nanoelectromechanical systems Switches Capacitors Logic gates Buck converters System-on-chip

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A rate selection algorithm for quantized undithered dynamic supply voltage scaling (poster session) 00

A rate selection algorithm for quantized undithered dynamic ...

引用

Proceedings of the 2000 international symposium on Low power electronics and design

作者： Lama H. Chandrasena Michael J. Liebelt Dept. of Electrical and Electronic Engineering The University of Adelaide Adelaide SA 5005 Australia

ISBN: (纸本)9781581131901

In this paper we propose a novel rate calculation algorithm called Quantized Rate Selection (QRS) for quantized undithered dynamic supply voltage scaling (DSVS) systems. The algorithm monitors the total buffered workload, and where possible selects a rate value equal to a quantized rate value. At quantized rate values, energy dissipation of quantized DSVS systems approaches continuous voltage level DSVS systems. Our experimental work on FMIDCT computation using nine video sequences and a 4-level quantized undithered system shows that additional energy savings of 1.4% to 18.5% can be achieved from QRS, compared to the existing averaging technique.

关键词： averaging

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A monolithic V-band upconverter using 0.2 mu m InGaAs/GaAs pseudomorphic HEMT technology

A monolithic V-band upconverter using 0.2 mu m InGaAs/GaAs p...

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Microwave, MTT-S International symposium

作者： H. Wang B. Nelson L. Shaw R. Kasody Y. Hwang W. Jones D. Brunone M. Sholly J. Maguire T. Best Electronic Systems Group TRW CA USA TRW Redondo Beach CA USA

The authors present the design and performance of a complete monolithic upconverter macrocell using 0.2- mu m InGaAs/GaAs pseudomorphic high electron mobility transistor (HEMT) technology. Individual components, including a 2-10-GHz IF amplifier, a V-band upconverting mixer, and a V-band amplifier are also described. Both linear and nonlinear circuit simulations were performed during the design to predict the circuit performance. The measured results demonstrated a conversion gain of 10 dB at V-band by injecting the 2-10-GHz IF frequency with a local oscillator drive of 10 dBm at 54 GHz.< >

关键词： HEMTs Macrocell networks Indium gallium arsenide Gallium arsenide PHEMTs Electron mobility MODFETs Nonlinear circuits Predictive models Circuit simulation

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The HDL and FE Thermal Modeling of Heterogeneous systems

The HDL and FE Thermal Modeling of Heterogeneous Systems

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： G. Janczyk T. Bieniek Institute for Electron Technology Warsaw Poland

Advanced heterogeneous systems are fabricated in dedicated technologies. If a designer attempts to integrate standalone devices into one heterogeneous system, some particular problems of the mixed modeling appear. This paper discusses the problem and presents a novel method of the desired model generation and the device simulation.

关键词： Hardware design languages Iron Mathematical model Assembly Semiconductor device modeling Electrons Optimization methods Baseband Sensor systems Foundries

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Leakage optimization using transistor-level dual threshold voltage cell library

Leakage optimization using transistor-level dual threshold v...

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ieee International symposium on Quality electronic design

作者： Chandra S. Nagarajan Lin Yuan Gang Qu Barbara G. Stamps Cisco Systems Inc. San Jose CA USA Synopsys Inc. Mountain View CA USA University of Maryland College Park MD USA Atmel Corporation Columbia MD USA

Recently, a transistor level dual-V th technique has been proposed, where transistors within the same cell are allowed to have different V th to form the so-call mixed V th (MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual V th design flow. To make this practical, current approach adds another design phase after technology mapping to replace high leakage cells with their low leakage MVT variants. We propose a method to seamlessly and effectively integrate transistor-level dual V th technology into existing low power design flow. This paper reports our successful experience in applying this method to optimize leakage under timing constraints in an industrial design environment. For demonstration purpose, we build an MVT library based on only 15 cells in a standard library that contains 590 cells. On 11 ISCAS benchmarks and three industrial designs, this MVT library optimizes 27% of the design. Yet it gives an average of 9% and up to 25% leakage saving over the state-of-art gate level dual V th design with a full size high V th library.

关键词： Threshold voltage Libraries circuits Delay Timing CMOS technology Constraint optimization design optimization Batteries Costs

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Security Analysis of a New FPE Stream Cipher

Security Analysis of a New FPE Stream Cipher

引用

ieee International symposium on circuits and systems (ISCAS)

作者： A. Pérez-Resa M. Garcia-Bosque C. Sánchez-Azqueta S. Celma Group of Electronic Design Zaragoza University Zaragoza Spain

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

In some encryption systems it is necessary to preserve the format and length of the encrypted data. This kind of encryption is called FPE (Format Preserving Encryption) or DPE (Datatype Preserving Encryption). For example, in the case of PCS (Physical Coding Sublayer) at Gigabit Ethernet optical communications, the 8b10b symbol flow can be encrypted at line rate thanks to a symmetric encryption scheme that must preserve the format and coding properties of 8b10b symbols. In this case, since a high speed data flow needs to be encrypted preserving its format, the usage of an FPE stream cipher could be advantageous. For this purpose, a new keystream generator scheme is proposed in this work. It is based on a secure block cipher working in CTR (Counter) mode whose output is subjected to a modulo operation. Moreover, a security analysis for this mode is carried out, deriving an expression for the IND-CPA (Indistinguishability under Chosen Plaintext Attack) advantage of any adversary, concluding that this mode can be considered secure in the same way as traditional modes are. Furthermore, the proposed structure has been implemented over an FPGA (Field Programmable Gate Array) device and adapted to a Gigabit Ethernet application.

关键词： Games Ciphers Encryption Field programmable gate arrays Encoding

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Investigations into RF MEMS switches for reconfigurable phased antenna arrays

Investigations into RF MEMS switches for reconfigurable phas...

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Antennas and Propagation Society International symposium

作者： J. Poon Lie Chen Ling N.C. Karmakar Division of Communication Engineering School of Electrical and Electronic Engineering Nanyang Technological University Singapore

This paper presents the parametric study of a low-loss RF-MEMS shunt capacitive switch suitable for reconfigurable phased array antennas. The inductively tuned switch design is analyzed on the HP-ADS Momentum. The width and the height of the air bridge and the CPW line gap hence the bridge length are the three parameters of the switch that are varied to investigate the switch performance from 1 GHz to 40 GHz. Simulated results show that the isolation and return loss of the switch can be optimized by changing the three abovementioned parameters. The switch yields very high isolation and return loss in the order of 50 dB and very tow insertion loss in the order of 0.2 dB over a very large frequency range.

关键词： Phased arrays Radiofrequency microelectromechanical systems Switches Antenna arrays Bridge circuits Coplanar waveguides Contacts Frequency Conducting materials Bandwidth

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