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Realisation of binary associative memories using standardised current mode analogue building blocks

Realisation of binary associative memories using standardise...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： D. Grant P.K. Houselander J.T. Taylor Department of Electronic & Electrical Engineering University College London UK

An analogue current mode design methodology is presented for the implementation of binary associative memories. Thus, by using the Hamming feedforward network as an example of a binary associative memory and efficiently mapping it into two CMOS-VLSI building block configurations, a prototype artificial neural network (ANN) is developed. The IC building blocks utilize the characteristics of the subthreshold region and converge to a classification in one pass, requiring no feedback. The result is an analog network with the desirable features of high integration, low circuit complexity, and low power dissipation.< >

关键词： Artificial neural networks Integrated circuit modeling Associative memory Semiconductor device modeling Analog integrated circuits Integrated circuit interconnections Power dissipation Integrated circuit noise Prototypes Complexity theory

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design for manufacturability for electronic design: a system for evaluating printed circuit design tradeoffs

Design for manufacturability for electronic design: a system...

引用

ieee/CHMT(CPMT) International electronics Manufacturing Technology symposium

作者： W. Tani Printed Circuit Division Research and Development Hewlett Packard Company Palo Alto CA USA

A system for evaluating printed circuit design (PCD) tradeoffs during the electronic design process has been developed. The system consists of a stand-alone PC-based software tool and support documentation which describes system operation, content, methodology, optimization processes, and printed circuit technology selection criteria. At any stage of the PCD process, the system can be used to evaluate the advantages and disadvantages of potential board design alternatives. Example design tradeoffs include board cost vs. circuit density, electrical performance vs. cost, and cost vs. manufacturability. All tradeoffs are based on a set of models and metrics which predict board density and technology requirements, board cost, fabrication yield, and expected electrical performance ranges. System models and metrics are based on actual production fabrication capabilities. The system's potential for significantly reducing overall PCD cycle times while simultaneously satisfying overall board design constraints has been demonstrated.< >

关键词： Manufacturing Costs Printed circuits Fabrication Process design Software tools Documentation Optimization methods Predictive models Production systems

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Simultaneous magnitude and group delay approximation for IIR filters via balanced model reduction

Simultaneous magnitude and group delay approximation for IIR...

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ieee International symposium on circuits and systems (ISCAS)

作者： I. Kale G.D. Cain B. Salome B. Beliczynski School of Electronic and Manufacturing Systems Engineering Polytechnic of Central London London UK Ecole Superieure de Technologie Electrique Groupe ESIEE Noisy le Grand France Institute of Control and Industrial Electronics Warsaw University of Technology Warsaw Poland

A technique for designing IIR (infinite impulse response) filters to simultaneously meet arbitrary magnitude and group delay specifications, without explicit equalizer sections, through the use of balanced model reduction is described. FIR (finite impulse response) design tools which make the approximation task relatively easy are employed prior to an FIR-to-IIR conversion process. The use of this reduction algorithm in a real-time FIR system identification and subsequent IIR compensation scene is also reported.< >

关键词： Delay IIR filters Reduced order systems Finite impulse response filter Prototypes Industrial electronics Layout Digital filters Fourier series Frequency

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VLSI system compiler for digital signal processing: Extended modularization and placement

VLSI system compiler for digital signal processing: Extended...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： K. Ito T. Shimizu H. Kunieda Department of Electrical and Electronic Engineering Tokyo Institute of Technology Tokyo Japan

A VLSI system compiler which generates a highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms is described. It consists of several stages to convert processing algorithms into a suitable one for VLSI implementation. An extended modularization and a placement of general digital signal processing algorithms are proposed as parts of the VLSI system compiler. A novel modularization algorithm is presented which will homogenize operations in DSP (digital signal processing) algorithms of a wider input class than before. A placement algorithm is developed which embeds inner-product processors with the requirement of random interprocessor communications into a rectangular processor array without losing the inherent highly parallel processing nature.< >

关键词： Very large scale integration Digital signal processing Signal processing algorithms Optimal scheduling Processor scheduling Digital signal processing chips Signal design Flow graphs Throughput Routing

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Multiple bus networks based on block designs

Multiple bus networks based on block designs

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ieee International symposium on circuits and systems (ISCAS)

作者： W.W.-M. Dai Y. Kajitani Y. Hirata Computer Engineering Board of Studies University of California Santa Cruz CA USA Department of Electrical and Electronic Engineering Tokyo Institute of Technology Japan

Proposes a class of multiple bus networks with O(n) processors and O(n) buses, in which each bus connects to O( square root n) processors and each processor connects to O( square root n) buses. The networks are single-hop: any two processors are connected to exactly one bus. The authors prove that the multiple buses with constant fanout and constant bus loading are the best in terms of bus-time product. For those networks with n processors whose existence is unknown or has been disproved, the authors construct relaxed networks with small skew in bus-loading. The proposed multiple bus networks match well with the multichip module technology.< >

关键词： design engineering Signal processing Computer networks Multichip modules Switches Communication switching Spread spectrum communication Telecommunication network reliability Delay Maintenance

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An adaptive image encoding technique using pyramid architecture

An adaptive image encoding technique using pyramid architect...

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ieee International symposium on circuits and systems (ISCAS)

作者： M. Nasipuri S. Roy S. Misra D.K. Basu Department of Computer Science & Engineering Jadavpur University Calcutta India

An adaptive block truncation encoding scheme is described. The adaptive block size encoding approach used removes the bottlenecks of compromising the reduction factor and fidelity of the decoded image present in the corresponding fixed block size scheme. The results show that the adaptive scheme produces a better reduction ratio, keeping approximately the same fidelity measure. The scheme is suitable for implementation with the pyramidal architecture which has a hierarchical nature of processing and needs greatly reduced logarithmic distances for passing information among the processing elements of the meshes. An added advantage of the present system is that it extracts most of the edge information and localizes it at the lowest mesh with respect to the host. This simplifies greatly the further processing of the image regarding its edges and regions.< >

关键词： Image coding Pixel Decoding Transform coding Computer architecture Computer science Encoding Data mining electronic design automation and methodology Predictive coding

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A new fast constraint graph generation algorithm for VLSI layout compaction

A new fast constraint graph generation algorithm for VLSI la...

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ieee International symposium on circuits and systems (ISCAS)

作者： J. Fang J.S.L. Wong K. Zhang P. Tang Electronics Engineering Department Fudan University Shanghai China Department of Electronic Engineering Hong Kong Polytechnic Institute Hong Kong China

A new fast constraint graph generation algorithm called the parallel plane sweep shadowing (PPSS) algorithm is presented for VLSI layout compaction. The algorithm is significant in two aspects. First, instead of analyzing each element shadow individually, PPSS estimates all element shadows simultaneously, which makes it more efficient to generate irredundant constraints. Second, instead of the conventional perpendicular plane sweep method, a parallel plane sweep scheme is developed. This reduces the number of events by half. The experimental results show that PPSS is linear in space and time complexity, and requires about one minute to build a graph from 10000 rectangles on a Sun 3/60 workstation.< >

关键词： Very large scale integration Compaction Shadow mapping Data structures Sun Workstations Algorithm design and analysis Integrated circuit layout Solid modeling Lamps

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Hybrid packaging technique for high power density circuit

Hybrid packaging technique for high power density circuit

引用

ieee symposium on Semiconductor Thermal Measurement and Management (SEMI-THERM)

作者： Ngon Binh Nguyen F.B. Jones Westinghouse Electronics Systems Group Baltimore MD USA

Downsizing or miniaturizing power circuits for the 1990's power conversion technologies requires high and very high power density (greater than 100 watt/in/sup 3/) packaging capability. Among different packaging techniques, the hybrid packaging technique is preferred for many applications because it has a good reliability history. This technique utilizes newly developed processes and materials such as direct bonded copper and diamond coated substrates to significantly improve thermal management and achieve optimal thermal resistance (less than 0.4 degrees C/watt). A 124 watt/cm/sup 2/ (800 watt/in/sup 2/) power density hybrid packaging example is presented here. The results of thermal design and evaluation of this hybrid are discussed.< >

关键词： Switches Thermal resistance Thermal management electronic packaging thermal management Switching circuits Temperature Copper Power conversion Bonding Power dissipation

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Programmable analog VLSI CNN chip with local digital logic

Programmable analog VLSI CNN chip with local digital logic

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ieee International symposium on circuits and systems (ISCAS)

作者： K. Halonen V. Porra T. Roska L. Chua Electronic Circuit Design Laboratory Helsinki University of Technology Espoo Finland Computer and Automation Institute Hungarian Academy of Sciences (ATOMKI) Budapest Hungary Berkeley Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA

A new integrated circuit cellular neural network (CNN) implementation having digitally or continuously selectable template coefficients is presented. Local logic and memory are added into each cell providing a simple dual (analog and digital) computing structure. The variable-gain operational transconductance amplifiers (OTAs) are used as the voltage controlled current sources to program the template element values. This analog array processor can be applied to solve problems with a sequence of different templates. A 4-by-4 CNN circuit is realized using the 2- mu m analog CMOS process. To test the circuit a general purpose control system was designed with the microcomputer interface.< >

关键词： Very large scale integration Cellular neural networks Logic Circuit testing Digital integrated circuits Analog computers Transconductance Operational amplifiers Voltage control CMOS process

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AN APPROACH TO LINEAR-PHASE APPROXIMATION THAT USES TIME DOMAIN CONSTRAINTS

AN APPROACH TO LINEAR-PHASE APPROXIMATION THAT USES TIME DOM...

引用

1990 INTERNATIONAL SYMP ON circuits AND systems ( ISCAS 90 )

作者： LIND, L Department of Electronic Systems Engineering University of Essex Colchester Essex UK

A design procedure for linear phase filters is presented. The ideal frequency-domain performance is transformed to the time domain. A realizable filter which has impulse-response zero crossings close to those of the ideal case is found. Computed results confirm the quality of this approximation method. The ideal zero crossings act as guides and give the desired control in both time and frequency domains.< >

关键词： Linear approximation Frequency domain analysis Function approximation Fourier transforms Poles and zeros Nonlinear filters Computer errors Passband Time factors design engineering

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