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A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology

A 40nm Low Power High Stable SRAM Cell Using Separate Read P...

引用

ieee International symposium on Nanoelectronic and Information systems (iNIS)

作者： Jitendra Kumar Mishra Harshit Srivastava Prasanna Kumar Misra Manish Goswami Department of Electronics and Communication Engineering Indian Institute of Information Technology Allahabad India

ISBN: (纸本)9781538691731;9781538691724

At lower technology, the static power dissipation and stability of conventional six transistors static random access memory (SRAM) cell poses a major issue. To address this issue, a novel eleven transistor (11T) SRAM cell for improving read stability and reducing the static power dissipation is proposed in this work. In the proposed 11T SRAM cell, the storing node isolates from the read bit line using separate read port while sleep transistor methodology is explored for power saving. With this the read static noise margin (RSNM) value of proposed design is enhanced by 6x, 2.3x, 2.7x and 1.3x when compared with basic 6T SRAM cell, 11T ST2 SRAM cell, 11T ST1 SRAM cell, ST11T SRAM cell respectively. The write stability is also enhanced by 1.6x over basic 6T SRAM cell, 1.14x over 11T SRAM and penalty of 1.17x when compared with other 11T SRAM cell. Further, using the sleep transistor methodology the static power consumption of the proposed design has been reduced by 4.6x when compared with basic 6T SRAM cell. The proposed 11T SRAM cell has been verified in 40nm CMOS technology node using cadence virtuoso tool.

关键词： SRAM cells Transistors Power dissipation Switching circuits Circuit stability Leakage currents Stability analysis

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A Convolutional Neural Network Accelerator Architecture with Fine-Granular Mixed Precision Configurability

A Convolutional Neural Network Accelerator Architecture with...

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ieee International symposium on circuits and systems (ISCAS)

作者： Xian Zhou Li Zhang Chuliang Guo Xunzhao Yin Cheng Zhuo College of Information Science and Electronic Engineering Zhejiang University Hangzhou China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Convolutional neural networks (CNNs) have been widely deployed in deep learning applications, especially on power hungry GP-GPUs. Recent efforts in designing CNN accelerators are considered as a promising alternative to achieve higher energy efficiency. Unfortunately, with the growing complexity of CNN, the demanded computational and storage resources for accelerators keep increasing, hindering its wider applications in mobile devices. On the other hand, many quantization algorithms have been proposed for efficient CNN training, which brings many small or zero weights. This is a unique opportunity for accelerator designers to employ much fewer bits, e.g., 4 bits, in both arithmetic core and storage, thereby saving significant design cost. However, such a single precision strategy inevitably compromises the accuracy as some key operations may demand a higher precision. Thus, this paper proposes a low power CNN accelerator architecture that can simultaneously conduct computations with mixed precisions and assign the appropriate arithmetic cores to operation with different precision demands. This proposed architecture can achieve significant area and energy savings, without accuracy compromise. The experimental results show that the proposed architecture implemented on FPGA can reduces almost half of the weight storage and MAC area, and lower the dynamic power by 12.1% when compared with a state-of-the-art CNN accelerator design.

关键词： Accelerator architectures Arrays Indexes Registers Convolutional neural networks

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Mixed-Signal DFT for fully testable ASIC

Mixed-Signal DFT for fully testable ASIC

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Frantisek Reznicek AMI Semiconductor Czech s.r.o. Brno Czech Republic

An efficient mixed-signal design strategy for test insertion standardization. The mixed-signal DFT (design For Test) strategy is built on three main linchpins: DFT and other design rules, DFT design structures and finally design to test interactions. Such a design strategy improves the overall device fault coverage which leads to minimal device failure rate on the customer side. This poster article explains first the design strategy in detail and finally highlights the reached results.

关键词： Application specific integrated circuits Circuit testing design for testability Ambient intelligence Circuit faults Automatic test pattern generation Current measurement Resistors Semiconductor device testing Standardization

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Common Mode Voltage Evaluation for choosing Quiet MCU and Optimizing PCB design: Electromagnetic Emissions Measurement for Integrated circuits

Common Mode Voltage Evaluation for choosing Quiet MCU and Op...

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ieee International symposium on Electromagnetic Compatibility (EMC)

作者： Atsushi Nakamura Yuichi Mabuchi Jisso Technology Development Department Renesas Technology Corporation Tokyo Japan Advanced Motor and Drive System Research and Development Center Hitachi Research Laboratory Hitachi Limited Hitachi Ibaraki Japan

Similar to the fact that the differential signaling interfaces radiate less amount than the typical single ended interfaces, radiation from wire harness connected to electronic control units using single chip micro computers can be reduced by adjusting the common mode voltage fluctuation of supply lines. The radiation from wire harness can be minimized when the Vcc and the Vss fluctuate with same magnitude in opposite phase. As estimating these fluctuations of real products using lots of components on complex PCB layout by simulation technique is quite difficult at this moment, alternative solution to investigate the common mode voltage fluctuation has been investigated. By the Workbench Faraday cage method and advanced usage of it with 180 deg four ports hybrid balun, common mode voltage fluctuations of Vcc and Vss with phase information can be monitored. Examples of this measured data are discussed and a way of reducing common mode radiation from wire harness is explained.

关键词： design optimization Electromagnetic measurements Integrated circuit measurements Wire Voltage fluctuations Variable structure systems Electromagnetic radiation Semiconductor device measurement Voltage control Microcomputers

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A PYNQ Evaluation Platform for FPGA Architectures of the Line Hough Transform

A PYNQ Evaluation Platform for FPGA Architectures of the Lin...

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Midwest symposium on circuits and systems (MWSCAS)

作者： David Northcote Louise H. Crockett Paul Murray Robert W. Stewart Department of Electronic and Electrical Engineering University of Strathclyde Glasgow Scotland UK

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

The Line Hough Transform (LHT) is an effective line detection algorithm for digital images. To meet real-time requirements, Field Programmable Gate Arrays (FPGAs) are often chosen to accelerate the LHT. However, many LHT architectures select different design parameters and discretisation steps for the Hough Parameter Space (HPS). The work presented in this paper describes a novel evaluation platform for FPGA architectures of the LHT. Our system is named the Hough Evaluation Platform (HEP) and can be used to visualise and inspect the HPS produced from LHT architectures that use different design parameters. Architectures are compared by evaluating the HPS using a unique measurement named the Peak to Mean Vote Ratio (PMVR). Our system employs the PYNQ framework on a Xilinx Zynq MPSoC device for the visualisation of the HPS and also determines the processing time of a given LHT architecture. The HEP has been implemented on a XCZU7EV-2e device and can operate up to a target frequency of 250 MHz.

关键词： Computer architecture Image edge detection Field programmable gate arrays Visualization Software Hardware Transforms

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Systematic design and Yield Optimization of RF and Millimeter-Wave Oscillators Using Neuro-Genetic Algorithm

Systematic Design and Yield Optimization of RF and Millimete...

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Microwave, MTT-S International symposium

作者： P. Sen R. Mukhopadhyay S. Sarkar S. Pinel R. J. Pratap C.-h. Lee J. Laskar Georgia Electronic Design Center School of ECE Georgia Institute of Technology Atlanta GA USA Intel Corporation Chandler AZ USA Samsung RFIC Design Center Georgia Technology Research Institute Atlanta GA USA

This paper presents a systematic procedure to optimize the design of RF and millimeter wave (MMW) integrated oscillators, and, at the same time, to maximize their yield using a neuro-genetic algorithm for the design centering. The design optimization procedure has been explained and demonstrated using a multi-band switched-inductor Colpitts VCO as well as a 30GHz cross-coupled VCO. The significance of the layout parasitic components in MMW oscillators has been described. An extended optimization procedure has been derived based on the sensitivity analysis involving the design components as well as the estimated layout parasitic elements. The pre-fabrication design yield for the given specifications is maximized using a genetic algorithm with neural models for the active circuit. The design yield is improved up to 90% with the developed neuro-genetic procedure

关键词： Algorithm design and analysis design optimization Radio frequency Voltage-controlled oscillators circuits Millimeter wave technology Wireless sensor networks Sensitivity analysis Genetic algorithms Production systems

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SoCECT: System on Chip Embedded Core Test

SoCECT: System on Chip Embedded Core Test

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Michael Higgins Ciaran MacNamee Brendan Mullane Department of Electronic & Computer Engineering (Mixed Signal Integrated Circuit Group) University of Limerick Ireland

This paper presents SoCECT (System on Chip Embedded Core Test), a novel test controller architecture that allows multiple ieee 1500 wrapped cores within a SoC to be tested concurrently. SoCECT makes use of the ieee 1149.1 JTAG state machine to operate the test controller and also to allow for future integration with an ieee P1687 interface. SoCECT also includes a Test Access Mechanism (TAM) methodology(distributed architecture) that reuses the physical connections of the SoC system bus to provide an efficient transport medium for structural and functional test vectors between the embedded test controller and ieee 1500 wrapped cores.

关键词： System-on-a-chip System testing Circuit testing Integrated circuit testing Logic testing Automatic testing System buses Integrated circuit interconnections Control systems Silicon

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Double-Stage Gate Drive Circuit for Parallel Connected IGBT Modules

Double-Stage Gate Drive Circuit for Parallel Connected IGBT ...

引用

ieee symposium Power Modulator

作者： D. Bortis P. Steiner J. Biela J.W. Kolar Power Electronic Systems Laboratory ETH Zurich Switzerland

In more and more pulsed power applications solid state modulators are applied. There, often IGBT modules must be connected in parallel due to their limited power handling capability. For balancing the currents in the IGBTs a control method adapting the gate signal of the single IGBTs has been presented in a previous paper. Besides the current balancing also the fall and rise times of the voltages/currents are crucial as they significantly influence the pulse shape and the modulator efficiency. For reducing the rise time of the pulse without increasing the maximal over-voltage of the IGBT a double-stage gate driver for parallel connected IGBTs is presented in this paper. In this gate driver also protection circuits for avoiding over-voltages as well as over-currents are included and an improved current balancing method is incorporated. Finally, measurement results revealing the dependency of the rise time/turn off losses on the design parameters of the gate drive are presented.

关键词： Insulated gate bipolar transistors Pulse modulation Driver circuits Solid state circuits Voltage Pulse shaping methods Shape Protection Loss measurement Time measurement

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AxMOD: VLSI Modular Reduction design Exploring Approximate Arithmetic Units

AxMOD: VLSI Modular Reduction Design Exploring Approximate A...

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symposium on Integrated circuits and systems design (SBCCI)

作者： Lourenço Mulling Morgana M. A. Rosa Rafael Soares Eduardo Costa Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

This work investigates the design of approximate arithmetic operator units used in the VLSI modular reduction (AxMOD) architecture. The AxMOD architecture herein proposed explores the following arithmetic operators: i) two approximate iterative-based fixed-point and Goldschmidt (GLD) dividers, ii) five approximate adders (AxA): COPY adder, error-tolerant adder (ETA), lower-part OR adder (LOA), truncation (Trunc), and approximate parallel prefix adder (AxPPA), and iii) five approximate multipliers of approximate radix-4 multiplier units (AxRMU), dynamic range unbiased multiplier (DRUM), rounding-based approximate (RoBA), truncated multiplier (Trunc), and the leading one-bit based approximate (LoBA). Our demonstration of AxMOD’s efficiency using approximate arithmetic operators from the Pareto-optimal front illustrates the area and power-quality trade-off. Our results reveal that in fixed-point arithmetic, AxRMU with K = 16 and Trunc adder with K = 8 deliver energy savings of up to 4.14× compared to the state-of-the-art.

关键词： Energy consumption Accuracy Energy conservation Power quality Very large scale integration Dynamic range Adders System analysis and design Fixed-point arithmetic

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Analytical dynamic time delay model of strongly coupled RLC interconnect lines dependent on switching

Analytical dynamic time delay model of strongly coupled RLC ...

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ieee International symposium on Quality electronic design

作者： Seongkyun Shin Yungseon Eo W.R. Eisenstadt Jongin Shim Department of Electrical and computer Engineering Hanyang University Ansan Kyunggi South Korea Department of Electrical and computer Engineering University of Florida Gainesville FL USA

In today's UDSM(ultra-deep-sub-micron)-process-technology-based ICs, dynamic delay variations of strongly coupled lines (due to neighboring net switching activity) make static timing analysis problematic. In this paper, new analytical timing models for RLC coupled lines are presented and their accuracy is verified. Coupled interconnect lines are decoupled into an effective single line model by using effective capacitances and effective inductances corresponding to switching activity. Their signal transient waveforms of the effective single line models are determined by exploiting the TWA (Traveling-wave-based Waveform Approximation) technique. This is followed by single line analytical timing model development. It is shown that the models have excellent agreement with SPICE simulations for various circuit performance parameters such as line pitch, line length, driver/receiver size, IMD-thickness, and aspect ratio.

关键词： Coupled mode analysis Delay effects Timing Integrated circuit interconnections Analytical models Capacitance SPICE Circuit simulation Circuit optimization Driver circuits

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