The preliminary design details for two sapphire whispering gallery mode phase stabilizers are presented. The sapphire resonators are cooled in individual liquid nitrogen dewars to an operating temperature of approxima...
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The preliminary design details for two sapphire whispering gallery mode phase stabilizers are presented. The sapphire resonators are cooled in individual liquid nitrogen dewars to an operating temperature of approximately 80 K. Each operates to stabilize the phase of an 8.1 GHz signal derived from a quartz crystal oscillator operating at 100 MHz. Ultra-low phase noise (-80 dB/Hz at 1 Hz offset) is projected due to the high resonator Q (3 × 107 at 80 K). The temperature of the thermally uncompensated sapphire resonators is stabilized by RF heating to a value approximately 3 degrees above that of a liquid nitrogen bath. Oscillator configurations which can further reduce oscillator phase noise are discussed and analyzed. These circuit improvements should provide crystal-oscillator type performance in a room-temperature 10 GHz (X-band) oscillator using a whispering gallery mode sapphire resonator with an intrinsic Q of 2 × 105. A general description of the oscillator systems and the thermal design considerations together with design details and analysis for the microwave aspects is presented.
It is shown that computational inefficiency can be avoided by combining the individual subnetworks two at a time, and calculating the S-parameters each time a connection is made, until the complete network is assemble...
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It is shown that computational inefficiency can be avoided by combining the individual subnetworks two at a time, and calculating the S-parameters each time a connection is made, until the complete network is assembled. This technique, called the subnetwork growth method, has the advantage that no large sparse matrices are created. In making a connection there are two distinct operations, depending on whether the ports to be joined are on different networks or on the same network. Formulas for the new S-parameters can be calculated using signal flow graphs. To demonstrate the subnetwork growth method, a microstrip CAD package called Puff has been developed. The circuit description in Puff is stored as dynamic variables that are addressed using pointers. The process of laying out a network consists of building up a linked list of subnetworks and connections. In the analysis stage, Puff collapses these linked lists by making connections until no joints remain. To illustrate a practical design, a simple microstrip low-pass filter, namely, a three-stage low-pass Tchebyscheff filter with a 0.1-dB ripple, is built.
It is pointed out that the multichip module on cofired ceramic substrate is a promising technology for high-performance systems. The reduction of feature size and the possibility of obtaining vias and conductors at th...
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It is pointed out that the multichip module on cofired ceramic substrate is a promising technology for high-performance systems. The reduction of feature size and the possibility of obtaining vias and conductors at the same pitch allow increased density and wiring flexibility. However, vias crossing through several levels at fixed positions reduce connectivity to such an extent that they occupy two places on each metal level with conventional technology. design considerations for improving the density and processing in order to obtain stacked vias are discussed. It is shown that a judicious distribution of fixed trough vias allows a reduction of the pitch of the chips. In addition, when stacked vias are possible, the space needed for vias is reduced by almost 30%, leaving better availability for wiring.
A relatively simple high-voltage (HV) buck regulator circuit using a series crossatron switch tube is presented. Implementation of the buck regulator circuit led to a HV sensor investigation. This investigation result...
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A relatively simple high-voltage (HV) buck regulator circuit using a series crossatron switch tube is presented. Implementation of the buck regulator circuit led to a HV sensor investigation. This investigation resulted in a novel high-voltage sensor circuit using an FET as a constant current source. The novel sensing and logic circuit samples the pulse discharge capacitor voltage and generates turn on/turn off triggers to the series crossatron switch tube to control the recharge time of the pulse discharge capacitor. Circuit analysis by Fortran programming and P-splice analysis indicate that the buck regulator design goal of 0.02% HV regulation can be met under the worst conditions of line and load variations and high PRF (pulse repetition frequency) stagger ratios.
An overview of electrical and mechanical aspects of electronic packaging as they pertain to midrange and high-end computer systems is presented. Continued advances in semiconductor technology and manufacturing tools h...
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An overview of electrical and mechanical aspects of electronic packaging as they pertain to midrange and high-end computer systems is presented. Continued advances in semiconductor technology and manufacturing tools have fueled the expectation for continued greater function, higher performance, and lower costs in electronicsystems. To meet this expectation, parallel progress in electronic packaging technology is necessary to realize the benefits of the VLSI technology advancements. Electrical and mechanical aspects of the electronic packaging structure-from the increased circuits per chip to the physical design of the electronic packaging-and future directions in packaging evolution are discussed. Innovations in single-chip and multichip modules, as well as the driving forces from the electrical requirements to the need of the physical design to meet wiring and performance demands are considered.< >
The application of formal methods to the specification and design derivation of integrated circuits is addressed. The initial specification is expressed as an abstract relation between data tuples. This relation is a ...
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The application of formal methods to the specification and design derivation of integrated circuits is addressed. The initial specification is expressed as an abstract relation between data tuples. This relation is a combination of conditional statements and associated data actions. Structural circuit descriptions are derived by step-wise application of proven laws to the specification while maintaining behavioral equivalence. This yields designs that are correct by construction. An example of a simple microprocessor design is used to illustrate the method.< >
To improve the offset and noise performances of CMOS amplifiers, several BiCMOS operational amplifiers with bipolar junction transistors (BJTs) applied in the input stage are presented. The speed performance of the am...
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To improve the offset and noise performances of CMOS amplifiers, several BiCMOS operational amplifiers with bipolar junction transistors (BJTs) applied in the input stage are presented. The speed performance of the amplifiers is improved. The input stage bias current is optimized for minimum noise as a function of the source resistance. Measurements on the realized BiCMOS amplifiers confirm the theory. In integrated circuits the theory allows the amplifier noise performance to be optimized because both the source resistance and the bias current of the amplifiers can be designed.< >
Various aspects of the design of a high-speed GaAs switched-capacitor filter are discussed. The circuit is based on a formerly unexploited finite-region insensitive integrator-pair, taking advantage of a recently reco...
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Various aspects of the design of a high-speed GaAs switched-capacitor filter are discussed. The circuit is based on a formerly unexploited finite-region insensitive integrator-pair, taking advantage of a recently recognized property of its inverting integrator. Device modeling and the influence of transistor characteristics on subcircuit design are discussed. Details of the filter-optimization procedures are given. The circuit has been fabricated and is now being mounted for testing.< >
The feedback linearizing control for designing a nonlinear exciter is reviewed. Pseudolinearizing control for designing a nonlinear exciter is proposed for the first time. General mathematical conditions under which f...
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The feedback linearizing control for designing a nonlinear exciter is reviewed. Pseudolinearizing control for designing a nonlinear exciter is proposed for the first time. General mathematical conditions under which feedback linearizing and pseudolinearizing controls are equivalent are introduced. The theoretical results are illustrated using an exciter design example. The necessary mathematical background is provided.< >
A new algorithm for finding all DC solution points of nonlinear circuit equations is presented. The algorithm makes use of interval analysis techniques. Unlike other known algorithms, the present algorithm guarantees ...
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A new algorithm for finding all DC solution points of nonlinear circuit equations is presented. The algorithm makes use of interval analysis techniques. Unlike other known algorithms, the present algorithm guarantees that all components of solution set M contained in an initial bounded rectangular region will be found within a prescribed accuracy. Moreover, the new algorithm requires far less computer time.< >
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