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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Ultra-broadband nonlinear PHEMT modelling using TOPAS/sup TM/

Ultra-broadband nonlinear PHEMT modelling using TOPAS/sup TM...

引用

ieee Workshop on, High Performance Electron Devices for Microwave and Optoelectronic Applications

作者： D.S. McPherson K. Elgaid I.G. Thayne I.D. Robertson S. Lucyszyn Microwave Systems Research Group Department of Electronic Engineering University of Surrey Surrey UK Nanoelectronics Research Centre Department of Electronics and Electrical Engineering University of Glasgow Glasgow UK

ISBN: (纸本)078036550X

This paper presents the use of a nonlinear TOPAS/sup TM/ model to describe the behaviour of an AlGaAs/InGaAs/GaAs PHEMT device. The extracted model features excellent agreement at DC and for small-signal excitation up to 120 GHz. The model is implemented by the IMST for Agilent EDA's Series IV/sup TM/ and ADS/sup TM/ circuit simulators.

关键词： PHEMTs Circuit simulation Gallium arsenide Nonlinear circuits Scattering parameters Nanoelectronics Feature extraction electronic design automation and methodology MMICs Analytical models

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Common Mode Voltage Evaluation for choosing Quiet MCU and Optimizing PCB design: Electromagnetic Emissions Measurement for Integrated circuits

Common Mode Voltage Evaluation for choosing Quiet MCU and Op...

引用

ieee International symposium on Electromagnetic Compatibility (EMC)

作者： Atsushi Nakamura Yuichi Mabuchi Jisso Technology Development Department Renesas Technology Corporation Tokyo Japan Advanced Motor and Drive System Research and Development Center Hitachi Research Laboratory Hitachi Limited Hitachi Ibaraki Japan

Similar to the fact that the differential signaling interfaces radiate less amount than the typical single ended interfaces, radiation from wire harness connected to electronic control units using single chip micro computers can be reduced by adjusting the common mode voltage fluctuation of supply lines. The radiation from wire harness can be minimized when the Vcc and the Vss fluctuate with same magnitude in opposite phase. As estimating these fluctuations of real products using lots of components on complex PCB layout by simulation technique is quite difficult at this moment, alternative solution to investigate the common mode voltage fluctuation has been investigated. By the Workbench Faraday cage method and advanced usage of it with 180 deg four ports hybrid balun, common mode voltage fluctuations of Vcc and Vss with phase information can be monitored. Examples of this measured data are discussed and a way of reducing common mode radiation from wire harness is explained.

关键词： design optimization Electromagnetic measurements Integrated circuit measurements Wire Voltage fluctuations Variable structure systems Electromagnetic radiation Semiconductor device measurement Voltage control Microcomputers

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Double-Stage Gate Drive Circuit for Parallel Connected IGBT Modules

Double-Stage Gate Drive Circuit for Parallel Connected IGBT ...

引用

ieee symposium Power Modulator

作者： D. Bortis P. Steiner J. Biela J.W. Kolar Power Electronic Systems Laboratory ETH Zurich Switzerland

In more and more pulsed power applications solid state modulators are applied. There, often IGBT modules must be connected in parallel due to their limited power handling capability. For balancing the currents in the IGBTs a control method adapting the gate signal of the single IGBTs has been presented in a previous paper. Besides the current balancing also the fall and rise times of the voltages/currents are crucial as they significantly influence the pulse shape and the modulator efficiency. For reducing the rise time of the pulse without increasing the maximal over-voltage of the IGBT a double-stage gate driver for parallel connected IGBTs is presented in this paper. In this gate driver also protection circuits for avoiding over-voltages as well as over-currents are included and an improved current balancing method is incorporated. Finally, measurement results revealing the dependency of the rise time/turn off losses on the design parameters of the gate drive are presented.

关键词： Insulated gate bipolar transistors Pulse modulation Driver circuits Solid state circuits Voltage Pulse shaping methods Shape Protection Loss measurement Time measurement

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design of up conversion mixer with enhanced transconductance stage and low power consumption oscillator

Design of up conversion mixer with enhanced transconductance...

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URSI International symposium on Signals, systems, and electronics (ISSSE)

作者： Chang-Hsi Wu Guan-Xiu Jian Department of Electronic Engineering Lunghwa University of Science and Technology Taoyuan Taiwan

A 5.2 GHz self-oscillating mixer (SOM) for ieee 802.11a WLAN transmitter, fabricated using CMOS 0.18μm process, is presented in this paper. The conversion gain of the proposed Mixer is mainly upgraded by an enhanced transconductance technique. To reduce the power consumption, the proposed voltage controlled oscillator (VCO) employs a complementarily cross-coupled architecture. Under 1.5 V and 0.6 V supply voltage of Mixer and VCO, respectively, the simulated results of the proposed Mixer reveal a conversion gain of 10.74 dB, input third-order intercept (IIP3) of -4.8dBm, phase noise of -116.2dBc/Hz at 1 MHz offset and tuning range of 4.615GHz~5.335GHz (14.12%) while total power consumption is only 7.3mW. The size of the chip is 0.741mm ×1.291mm.

关键词： Mixers Voltage-controlled oscillators Radio frequency CMOS integrated circuits Transconductance Phase noise Tuning

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A high frequency current mode ladder filter using multiple output lossless integrator

A high frequency current mode ladder filter using multiple o...

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ieee International symposium on Intelligent Signal Processing and Communication systems (ISPACS)

作者： S. Sa-ad D. Chaythong Department of Electronic Engineering Faculty of Engineering Rajamangala University of Technology Srivijaya RMUTSV Songkhla Thailand

This paper describes a current mode integrator and filter. The circuit can operate at high cutoff frequency and has low input impedance. The design of current mode integrator is based on a low input impedance current mirror with grounded capacitors. The integrator provides a building block for using in active filter circuits based on the doubly terminated LC ladder filter prototype. A 5 th order low pass active ladder filter using the integrator is designed as an example and simulated by H-SPICE using the standard 0.5 mum CMOS technology. The designed cutoff frequency of the filter is 200 MHz and can be electronically tuned from 90-250 MHz by varying the DC bias current. The input impedance of the filter is low (11 ohm). The power dissipation is 1.2 mW/pole and is very practical when operated with a voltage supply of 1.5 V.

关键词： Active filters Impedance Cutoff frequency CMOS technology Mirrors Capacitors Prototypes Circuit simulation Power dissipation Voltage

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Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection

Evaluating the Resilience of the Approximate Parallel Prefix...

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symposium on Integrated circuits and systems design (SBCCI)

作者： Eloisa Barros Morgana M. A. Rosa Rodrigo Lopes Leonardo Antonietti Eduardo Costa Rafael Soares Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan Horses (HTH) present significant risks. We propose a framework to inject HTH into approximate adders (AxAs), specifically the Approximate Parallel Prefix Adder (AxPPA), and assess their impact. The framework, implemented in MATLAB (code available at ***/MorganaMacedo/AxPPA_HTH), evaluates HTH injection into AxAs, analyzing error metrics (SSIM, NCC, MSE, MAE, and error-probability) and conducting logic-synthesis (LS) analysis to detect physical anomalies indicative of HTH presence. Our results demonstrate AxPPA’s resilience against HTH injection, with detection thresholds varying with approximation bit size. LS analysis shows AxPPA effectively detects HTHs across all bit approximations, outperforming LOA, particularly at K=16. AxPPA also achieves superior energy savings of 31.95% compared to LOA and notable area savings, highlighting its efficacy in HTH detection and performance optimization.

关键词： Measurement Hardware Trojan horses Security MATLAB Adders System analysis and design Optimization Resilience Testing

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NASA Electric Aircraft Testbed (NEAT) Reconfiguration to Enable Altitude Testing of Megawatt-Scale Electric Machines

NASA Electric Aircraft Testbed (NEAT) Reconfiguration to Ena...

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AIAA/ieee Electric Aircraft Technologies symposium (EATS)

作者： Joseph M. Haglage Thomas W. Brown NASA Electric Aircraft Testbed Lead Diagnostics and Electromagnetics Branch GE Aviation Cincinnati OH USA Lead Controls Engineer Advanced Technology Organization NASA Glenn Research Center Cleveland OH USA

ISBN: (数字)9781624106057

ISBN: (纸本)9781728186474

The NASA Electric Aircraft Testbed (NEAT) has been developed over the past four years in order to provide a testbed that enables end-to-end testing of multiple technologies that are required for the development of a hybrid-electric aircraft. NEAT has been designed to be reconfigurable, so that the facility can be used to test different technologies in appropriate ways. The testbed has recently been reconfigured from a powertrain test, to a megawatt-scale dynamometer inside of an altitude chamber. This configuration enables full-power testing of megawatt-scale components and systems under simulated altitude conditions. This paper discusses the reconfiguration design of NEAT, along with problems encountered and mitigations implemented during checkout testing to date.

关键词： electronic warfare aircraft altitude chamber ALTITUDE SIMULATION National Aeronautics and Space Administration Reconfiguration power of test configurability electric machines

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Emerging Josephson Junction/Graphene Device Technologies towards THz Signal Generation

Emerging Josephson Junction/Graphene Device Technologies tow...

引用

ieee International symposium on circuits and systems (ISCAS)

作者： Zachary Cochran Trond Ytterdal Akul Madan Maher Rizkalla Department of Electrical and Computer Engineering Indiana University-Purdue University Indianapolis Indianapolis IN 46202 USA Department of Electronic Systems Norwegian University of Science and Technology H⊘gskoleringen 1 7491 Trondheim Norway

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

A novel approach to merge superconducting Josephson Junction (JJ) devices with nanoscale Graphene devices in order to achieve high gain-bandwidth-product on the order of THz was addressed. JJs are ultra-fast devices that consist of two superconducting plates separated by a nanoscale layer of nonconducting material which exhibits quantum tunneling phenomenon. While JJ-based devices have existed since nearly 1962, interfacing them with standard electrical systems has been a challenge for several reasons, including operating temperature, switching speed, and low-signal sensitivity. In this study, we investigated the possibility of utilizing JJ's so-called AC-effect in order to generate high frequency signals that can be accommodated by high speed nanoscale devices. Graphene Nano Ribbon Field Effect Transistors (GNRFET) have been emphasized for their very high frequency operation that is appropriate to accommodate the very high switching speed of the JJ devices. The study is based on the AC JJ effet with generating a sinusoidal current whose frequency directly scales with voltage. For a single-stage GNRFET CS amplifier, a gain of 35.7dB with a bandwidth of 217GHz was achieved, while 10.8dB with a unitary gain of 2.5THz was also accomplished. The paper details the design and interfacing of the JJ with GNRFET devices, targeting high frequency signal generation on the order of hundreds of GHz to THz.

关键词： Junctions Graphene Josephson junctions Resistance High-temperature superconductors Capacitance

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Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling

Temperature-Aware Task Mapping for Energy Optimization with ...

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： M. Bao A. Andrei P. Eles Z. Peng Embedded Systems Laboratory Department of Computer and Information Science Linkoping University Sweden

Temperature has become an important issue in nowadays MPSoCs design due to the ever increasing power densities and huge energy consumption. This paper proposes a temperature-aware task mapping technique for energy optimization in systems with dynamic voltage selection capability. It evaluates the efficiency of this technique, based on the analysis of the factors that can influence the potential gains that can be expected from such a technique, compared to a task mapping approach that ignores temperature.

关键词： Dynamic voltage scaling Temperature Voltage control Energy consumption design optimization Power system modeling System-on-a-chip Frequency System-level design Processor scheduling

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The design of a low-power low-noise phase lock loop

The design of a low-power low-noise phase lock loop

引用

ieee International symposium on Quality electronic design

作者： Abishek Mann Amit Karalkar Lili He Morris Jones Department of Electrical Engineering San Jose State University Foundation CA USA

ISBN: (纸本)9781424464548

A phase lock loop is a closed-loop system that causes one system to track with another. More precisely, a PLL can be perceived as a circuit synchronizing an output signal with a reference or input signal in frequency as well as phase. High-performance phase lock loops are widely used within a digital system for clock generation, timing recovery, and to efficiently sequence operations and synchronize between function units and ICs As the digital system grows the role of phase lock loop increases. Achieving low jitter and phase noise in phase lock loop with less area and power consumption is challenging. The present research relates to characterization and redesign of individual blocks of Phase lock loop (PLL) to improve its characteristics. More specifically redesigning of individual blocks like: Phase Frequency Detector to reduce area and static phase error, Voltage to Current converter to linearly increase the current input to the current controlled oscillator, Current Controlled Oscillator to reduce phase noise, amplitude distortion, area and power consumption. We also introduce an additional feedback loop to increase the gain of the charge pump in a manner that linearizes the overall loop gain over wide bandwidth. The Results are substantial improvements in the PLL characteristics such as low jitter, phase noise, area and power consumption.

关键词： Phase locked loops Phase noise Energy consumption Frequency synchronization Digital systems Jitter Voltage control Oscillators Tracking loops circuits

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