A description is presented of the design and performance of the first balanced DC-biased millimeter-wave mixer with a wide (12-GHz) instantaneous RF/IF bandwidth. Relative to prior mixers, this mixer requires less loc...
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A description is presented of the design and performance of the first balanced DC-biased millimeter-wave mixer with a wide (12-GHz) instantaneous RF/IF bandwidth. Relative to prior mixers, this mixer requires less local oscillator (LO) drive and yet provides the superior intermodulation suppression provided by a balanced design. The mixer includes a unique IF output filter which avoids the reentry problems associated with conventional high/low-Z/sub 0/ designs. The mixer design is applicable to a new generation of electronic warfare systems which cover wide millimeter-wave bands with a small number of mixers and shared LOs.< >
The computer-aided fabrication environment (CAFE) is a software system being developed at MIT for use in the manufacture of integrated circuits. CAFE is intended to be used in all phases of process design, development...
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The computer-aided fabrication environment (CAFE) is a software system being developed at MIT for use in the manufacture of integrated circuits. CAFE is intended to be used in all phases of process design, development, planning, and manufacturing of integrated-circuit wafers. The CAFE architectural framework supports a wide variety of software modules, including both development tools and online applications. The key components of the CAFE architecture are the data model and database schema, the process flow and wafer representations, the user interface, and the application programming and database interfaces. All CAFE application modules store and retrieve persistent data through a common database interface layer. Interface wrappers provide seamless, transparent integration of external tools and packages which have their own internal data formats.< >
A 32 bit call-handling processor for an electronic switching system (ESS) capable of a 5.6 MIPS instruction execution rate is discussed. The processor uses a mixed architecture consisting of a reduced instruction set ...
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A 32 bit call-handling processor for an electronic switching system (ESS) capable of a 5.6 MIPS instruction execution rate is discussed. The processor uses a mixed architecture consisting of a reduced instruction set computer (RISC) and a complex instruction set computer (CISC) to economize the instruction execution, and features a four-stage two-way pipeline and local storage for the RISC and writable control storage for the CISC. To obtain reliability, availability, and serviceability, such functions as parity check/generation, microdiagnostic, and matcher have been incorporated within the chip. The chip contains about 160 K transistors within a chip size of 13.2*13.7 mm/sup 2/. A 1.2 mu m double-metal CMOS technology has been used. In designing the chip layout, a compromise between manual and automatic placing or routing was adopted which enabled a reasonably short design time.< >
Tolerances of electronic circuit parameters play an important role in our judgement of circuit functionality. They must be considered both at the circuit design and testing stages. A problem of tolerances in a symboli...
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Tolerances of electronic circuit parameters play an important role in our judgement of circuit functionality. They must be considered both at the circuit design and testing stages. A problem of tolerances in a symbolic network analysis is discussed. Topological analysis combined with operations on discrete random variables allows the behavior of a circuit with toleranced parameters to be predicted. Automatic simplification of symbolic network functions is used to facilitate operations on discrete variables representing network parameters. Illustrative examples are given.
A description is given of Nice, a general-purpose optimization system that can be coupled to a performance evaluator such as a circuit simulator to provide designers with optimization techniques for the adjustment of ...
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A description is given of Nice, a general-purpose optimization system that can be coupled to a performance evaluator such as a circuit simulator to provide designers with optimization techniques for the adjustment of the parameters of a design. Nice features a rich library of optimization algorithms as well as a powerful graphics interface. Multiple objectives and functional constraints can be described by means of a specialized optimization language. The coupling of Nice to the SPICE3 circuit simulator is presented, and an example of circuit optimization is shown. Nice exhibits satisfactory results and shows performances better than that of similar systems.
The authors propose a paradigm shift for digital spectrum analysis from a transform to a digital filter bank. With the digital filter bank, they gain an additional degree of freedom in the design of the windows, namel...
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The authors propose a paradigm shift for digital spectrum analysis from a transform to a digital filter bank. With the digital filter bank, they gain an additional degree of freedom in the design of the windows, namely, the window length can be specified independently of the DFT length. The authors also explain the problem of measurement aliasing when more than one component fall within the passband of a DFT bin. With this digital filter bank point of view, they design a flat-top window with very sharp roll-off, achieving excellent frequency resolution.< >
A relationship between the statistical design centering (SDC) approach to production yield optimization and the minimax circuit design is established. It is shown that both approaches can be combined into one coherent...
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A relationship between the statistical design centering (SDC) approach to production yield optimization and the minimax circuit design is established. It is shown that both approaches can be combined into one coherent methodology, using the same optimization algorithm, and leading either to the yield maximum or to the best fulfillment of the nominal target specifications. Moreover, any other intermediate design between these two extreme cases can be defined by the designer in a sense similar to the one used in L. A. Zadeh's fuzzy set theory (1965). This requires only a specific modification of the acceptability region (set) membership function. The proposed methodology is closely related to the income optimization approach to the SDC problem introduced by L. J. Opalski and M. A. Styblinski (ieee Trans. Comput. Aided design, vol. CAD-5, no. 2, pp. 346-360, 1986. Convolution smoothing techniques combined with stochastic approximation can be used to solve the problem.
Microwave balanced diode and GaAs MESFET mixers have been designed and simulated using a computer-aided procedure. Microstrip circuit implementations of these mixers have been built. Two types of microstrip couplers, ...
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Microwave balanced diode and GaAs MESFET mixers have been designed and simulated using a computer-aided procedure. Microstrip circuit implementations of these mixers have been built. Two types of microstrip couplers, branch-line and rat-race in ring form, were implemented in the design of the diode mixers. Practical measurements agree well with simulated computer results.
A novel algorithm based on an internal model of an objective function for seeking a global optimum is presented. By minimizing this internal model function, constructed by a stationary Gaussian process, the minima of ...
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A novel algorithm based on an internal model of an objective function for seeking a global optimum is presented. By minimizing this internal model function, constructed by a stationary Gaussian process, the minima of the objective function can be obtained after an extremely small number of objective function evaluations. The usefulness of this algorithm is demonstrated by several numerical examples and its application to circuit design. The computational overhead for the optimization procedure is low as the model function is based on a stationary Gaussian process.
A general technique for designing a module N asynchronous counter with 50% duty cycle output is developed using signal flow graph (SFG) analysis. One master oscillator can be used to generate several divide-by-two fre...
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A general technique for designing a module N asynchronous counter with 50% duty cycle output is developed using signal flow graph (SFG) analysis. One master oscillator can be used to generate several divide-by-two frequencies with 50% duty cycle outputs. This design approach eliminates the need to design a complicated circuit for synchronizing the required frequencies and also has some capability for reducing the jitter resulting from the use of two or more distinct frequencies at the same time. The suggested technique is general and straightforward and could be used to design a programmable asynchronous counter with several output frequencies.
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