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检索条件"任意字段=IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Parasitic Circus: On the Feasibility of Golden-Free PCB Verification

Parasitic Circus: On the Feasibility of Golden-Free PCB Veri...

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International symposium on Physical & Failure Analysis of Integrated circuits

作者： Maryam Saadat Safa Patrick Schaumont Shahin Tajik Department of Electrical and Computer Engineering Worcester Polytechnic Institute Worcester MA USA

ISBN: (数字)9798350360608

ISBN: (纸本)9798350360615

Printed circuit boards (PCBs) are an integral part of electronic systems. Hence, verifying their physical integrity in the presence of supply chain attacks (e.g., tampering and counterfeiting) is of utmost importance. Recently, tamper detection techniques grounded in impedance characterization of PCB's Power Delivery Network (PDN) have gained prominence due to their global detection coverage, non-invasive, and low-cost nature. Similar to other physical verification methods, these techniques rely on the existence of a physical golden sample for signature comparisons. However, having access to a physical golden sample for golden signature extraction is not feasible in many real-world scenarios. In this work, we assess the feasibility of eliminating a physical golden sample and replacing it with a simulated golden signature obtained by the PCB design files. By performing extensive simulation and measurements on an in-house designed PCB, we demonstrate how the parasitic impedance of the PCB components plays a major role in reaching a successful verification. Based on the obtained results and using statistical metrics, we show that we can mitigate the discrepancy between collected signatures from simulation and measurements.

关键词： Measurement Integrated circuits Machine learning algorithms Impedance measurement Printed circuits Supply chains Impedance

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Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology

Three Subthreshold Flip-Flop Cells Characterized in 90 nm an...

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Havard Pedersen Alstad Snorre Aunet Department of Informatics University of Oslo Oslo Norway

This paper examines three different flip-flop designs in subthreshold operation. All flip-flops are simulated in a 65 nm and 90 nm process with a supply voltage ranging from 125 mV to 1 V. Process variations are examined at different process corners. Successful operations of a PowerPC 603 flip-flop at all process corners with a supply voltage down to 125 mV is shown at 65 nm. The best PDP and EDP numbers of flip-flops design at V{sub}(DD) = 200 mV in this paper are 53.6 aJ and 0.88 yJs, respectively.

关键词： CMOS technology Flip-flops Power supplies Energy consumption Power dissipation Threshold voltage Leakage current Informatics Application software circuits

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Development of Fast 3D Parasitic Extraction using Hierarchical Method for Integrated circuits and Packages

Development of Fast 3D Parasitic Extraction using Hierarchic...

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2008 ieee Antennas and Propagation Society International symposium (APSURSI 2008), vol.1

作者： Yang Yi Shu Yan Vivek Sarin Weiping Shi Texas A and M University College Station TX USA Synopsys Inc. Mountain View CA USA

ISBN: (纸本)9781424420414

Fast and accurate 3D parasitic extraction is very important in design and verification of very large scale integration (VLSI) circuits and electronic packages. In this paper, we review our research in the parasitic extraction using preconditioned hierarchical method, which is a significant improvement over existing methods. For parasitic extraction, the matrix-vector products can be computed efficiently by the fast multipole approximation [1], the precorrected fast Fourier transform (FFT) method [2]. These methods reduce the time for each matrix-vector product to O(n) or O(nlogn) where n is the number of elements in discretization. However, solving the linear system is still a formidable task since n is very large. In 1998, we developed HiCap [3] (a Hierarchical algorithm for Capacitance extraction), which shows that there is a major advantage in using sparse systems over fast multipole method (FMM)-approximated dense systems. In 2004, we further proposed PhiCap [4] (a Preconditioned hierarchical algorithm for Capacitance extraction) which introduces an algebraic linear transformation to convert the linear system from HiCap, into an equivalent sparse system. By further exploiting the advantage of the sparsification in PhiCap, we presented RedCap [5] that solves a reduced capacitance system by reducing the sparse linear system to a small subsystem. RedCap does not require any iteration and avoids solving the original large system. Recently, we extend the techniques in PhiCap to develop PhiImp [6] (a Preconditioned hierarchical algorithm for Impedance extraction). PhiImp generates a sparse system by converting the dense linear system from the modified partial element equivalent circuit (PEEC) formula and constructs preconditioners based on incomplete LU factorization.

关键词： Capacitance Linear systems Impedance Approximation methods Data mining Conductors Data structures

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First tests and MonteCarlo simulations of a compton camera with Si-pad detectors and highly-segmented HPGe detectors

First tests and MonteCarlo simulations of a compton camera w...

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ieee symposium on Nuclear Science (NSS/MIC)

作者： D. Mengoni C.M. Petrache M. Fantuzi G. Ambrosi E. Fiandrini N. Dinu M. Ionica G. Prete R. Ponchia G. Bassato INFN Sezione di Perugia Perugia Italy Dipartimento di Fisica Università degli Studi di Camerino Perugia Italy INFN Sezione di Perugia Perugia Italy INFN Sezione di Perugia Università degli Studi di Perugia Perugia Italy INFN Sezione di Peugia Università degli Studi di Perugia Perugia Italy Laboratori Nazionali di Legnaro I.N.F.N. Legnaro Italy INFN Laboratori Nazionali di Legnaro Legnaro Italy

The impetuous progress of the detection systems in nuclear medicine are based on major improvements of the sensitivity of the new detector systems and on the highly-integrated low-noise associated electronics, offering valuable solutions for the diagnostic of premature biological lesions. Most of the presently available detectors for nuclear medicine employ mechanical collimation, which couples the detection sensitivity to the spatial resolution. The electronic collimation of Compton cameras can overcome this drawback, but drastically reduces the efficiency due to the coincidence measurement. However, the Compton imaging systems can offer advantages over the traditional ones and the study of innovative solutions involving the newest available detectors and electronics could lead to unexpectedly good results. Our goal is to design a Compton camera based on Si-pad detectors and ASIC electronics. We performed extensive Monte Carlo simulations for systems consisting of Si-pad detectors with various thickness and pad dimensions, as well as for different geometries. The various Si-pad detectors were characterized before the bonding to the ASIC electronics and the whole assembly was subsequently tested with a VA-DAQ acquisition system from IDEAS. The results of the characterization measurements and tests will be presented

关键词： Cameras Detectors Nuclear medicine Nuclear electronics Collimators Application specific integrated circuits electronic equipment testing Biological system modeling Medical simulation Lesions

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An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs

An Integrated Input Encoding and Symbolic Functional Decompo...

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Stanislaw Deniziak Mariusz Wisniewski Department of Computer Engineering Cracow University of Technology Cracow Poland Department of Computer Science Kielce University of Technology Kielce Poland

In this paper a method for decomposition of functions with multi-valued inputs is presented. Decomposition is performed simultaneously with encoding of symbolic values. In this way an impact of input encoding on decomposition efficiency is taken into consideration during optimization. The goal of our method is to find encoding that maximally simplifies functional decomposition. Experimental results showed that the presented method significantly reduces the cost of FPGA implementations for most evaluated benchmarks.

关键词： Encoding Field programmable gate arrays Costs Table lookup electronic mail Boolean functions Logic devices Optimization methods Computer science High level synthesis

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FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond

FS2K: A Forksheet FET Technology Library and a Study of VLSI...

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ieee International symposium on circuits and systems (ISCAS)

作者： Yunjeong Shin Daehyeok Park Dohun Koh Dongryul Heo Jieun Park Hyundong Lee Jongbeom Kim Hyunsoo Lee Taigon Song School of Electronic and Electrical Engineering Kyungpook National University (KNU) Daegu South Korea School of Electronics Engineering Kyungpook National University (KNU) Daegu South Korea

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

The semiconductor foundries are now mass-producing 3nm transistors. In this trend, many studies on 2nm node report the potential of future transistors such as forksheet FET (FSFET) from the device perspective. However, only a few studies report the impact of advanced transistors at the full-chip level. Thus, this study focuses on enlightening the potential of FSFET at the full-chip level in the 2nm process compared to the 3nm node currently in mass production. To do this, we present FS2K, the first public 2nm technology library in FSFET, which provides the following results: 1) The simple scaling with no variation in devices or interconnect achieves only about 10% power reduction and area reduction in 2nm processes for FSFET and Nanoshet FET (NSFET). 2) An optimal performance improvement in a 2nm node requires FSFET to be designed in a 4T standard cell that is 1-track reduced from 3nm. Our 2nm 4T-FSFET design achieves -29.5% area reduction and -31.9% power reduction compared to the existing 3nm process. Thus, we emphasize the importance of optimization not only in the device but also in the cell layout for future processes.

关键词： Performance evaluation Process design Visualization Field effect transistors Layout Very large scale integration Libraries

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A Trim-Free PVT Invariant Current Reference with 0.48% Process Inaccuracy Using VTH Tracking Approach

A Trim-Free PVT Invariant Current Reference with 0.48% Proce...

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Midwest symposium on circuits and systems (MWSCAS)

作者： Vishnu Kuncham Jalluri Ram Gopal V.S.S. Pradhith Aniketh Atmakuri Chetan Mittal Khanh M Le Zia Abbas International Institute of Information Technology Hyderabad India Analog Intelligent Design Inc. CA USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

The prevalence of MOSFETs in diverse electronic applications highlights their significance. However, the sensitivity of MOSFET threshold voltage to process variation poses a substantial challenge in achieving consistent device performance. This paper proposes a novel approach to overcome this challenge by employing a threshold voltage $(V_{TH})$ tracking circuit that tracks the variation in $V_{TH}$ . Our primary objective is to develop a current reference that remains invariant across process, voltage, and temperature (PVT) variations, eliminating the need for an external trimming circuit. This is achieved by the meticulous integration of V TH tracking circuit, CTAT generator, PTAT generator, and a current adder. By employing this design, a process variation $(\frac{\sigma}{\mu})$ of 0.48%, a temperature coefficient (TC) of ${210}{ppm}/^{\circ} {C}$ ‘ for a temperature range of $-{40}/^{\circ} {C}$ to ${120}^{\circ} {C}$ , and a line sensitivity of 1.6% is achieved over a voltage range of 1.6V - 3V. The proposed circuit occupies an area of ${0.013}{mm}^{{2}}$ : while consuming power of 56μW at a typical corner of ${27}^{\circ}{C}$ and a supply of 1.8V. The given circuit is implemented in a 180nm CMOS process node with a generated reference current of 61nA.

关键词： Temperature sensors Performance evaluation Temperature distribution MOSFET Electric potential Sensitivity Costs

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Application-aware LCA of semiconductors: Life-cycle energy of microprocessors from high-performance 32nm CPU to ultra-low-power 130nm MCU

Application-aware LCA of semiconductors: Life-cycle energy o...

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ieee International symposium on electronics and the Environment

作者： David Bol Sarah Boyd David Dornfeld ICTEAM Institute Université catholique de Louvain Louvain-la-Neuve Belgium Laboratory for Manufacturing and Sustainability University of California Berkeley USA

The exponential growth of the semiconductor industry raises serious environmental concerns. Accurate life-cycle data are critical for both appropriate product eco-design and life-cycle analysis (LCA) of new electronic applications. Previous semiconductor LCA efforts were based on generic studies dealing with an average component description such as microprocessors, DRAM or Flash memories without taking into account the broad application range of each component. In this paper, we show that accurate life-cycle data can only be obtained with an application-aware approach. We demonstrate this with a life-cycle energy evaluation of microprocessors for five different applications: from high-performance 32 nm CPUs for servers and laptops to low-power 45 nm processors for set-top boxes and smart phones to ultra-low-power 130 nm MCUs for wireless sensors. For each category, we model the energy of the CMOS processing steps for integrated circuit (IC) fabrication as well as the use phase energy demand including both active and stand-by modes. Results show that life-cycle energy varies by a factor 20000× between the high-performance and the ultra-low-power ends.

关键词： CMOS integrated circuits Servers Microprocessors Program processors Optical wavelength conversion Portable computers Smart phones

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Thermal management of harsh-environment electronics

Thermal management of harsh-environment electronics

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ieee symposium on Semiconductor Thermal Measurement and Management (SEMI-THERM)

作者： M. Ohadi Jianwei Qi Smart and Small Thermal Systems Laboratory CALCE Electronics Systems and Products Center Mechanical Engineering Department University of Maryland College Park College Park MD USA

As the trend of highly integrated electronics and simultaneous miniaturization escalates to include faster processors, more functions, and higher bandwidths, electronics continue to become more compact in response to size limitations and strict reliability requirements. The result is an increasing heat flux at both the component and circuit board levels. In the last decade, average power densities and heat dissipation rates have increased nearly two-fold. It is expected that heat flux levels in excess of 100W/cm/sup 2/ for commercial electronics and over 1000W/cm/sup 2/ for selected military high power electronics will soon become a realistic and immediate challenge to overcome. There is also a growing demand for more sophisticated and capable electronics used in harsh environment applications such as those found in defense, automotive and oil exploration systems. Thermal management of harsh environment electronics is vital to the successful design, manufacture, and tactical operation of a variety of electronic systems to meet the high temperature, environmental, reliability, and cost effectiveness requirements. This paper will look into fundamental characteristics and thermal management challenges for practical harsh environment electronics and will overview the most widely known, as well as emerging technology solutions for such applications. Future thermal management of harsh environment electronics at the chip, board and system levels will be also discussed. The paper concludes with a ranking of the potential applicability of these techniques according to several criteria, including cost, ease of use, thermal performance, and reliability concludes the paper.

关键词： Thermal management of electronics Thermal management Environmental management Costs Bandwidth Integrated circuit reliability Printed circuits Power electronics Automotive engineering Petroleum

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Code Coverage Analysis using High-Level Decision Diagrams

Code Coverage Analysis using High-Level Decision Diagrams

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Jaan Raik Uljana Reinsalu Raimund Ubar Maksim Jenihhin Peeter Ellervee Department of Computer Engineering Tallinn University of Technology Tallinn Estonia

The paper proposes a novel method of analyzing code coverage metrics on a system representation called High-Level Decision Diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and test pattern generation. Current paper presents a technique, where fast HLDD based simulation is extended to support seamless code coverage analysis. We show how classical code coverage metrics can be directly mapped to HLDD constructs. In addition, we introduce an observability coverage calculation method using HLDD models. Experiments on ITC99 benchmark circuits indicate the feasibility of the proposed approach.

关键词： Analytical models Computational modeling Test pattern generators Observability Pattern analysis Computer simulation Integrated circuit measurements design engineering Software testing Process design

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