The author surveys the characterization and sources of noise in digital systems. The principal methods of characterizing noise in digital systems, including jitter and bit-error rate (BER) specifications, are explaine...
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The author surveys the characterization and sources of noise in digital systems. The principal methods of characterizing noise in digital systems, including jitter and bit-error rate (BER) specifications, are explained, and the manner in which these are produced is described. The various sources of noise generated within, and coupled into, digital circuits are briefly reviewed. design guidelines for minimizing the effects of noise are then developed.
The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particular...
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The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.
The author presents an overview on how an integrated E/E system designed for assembly and service can help manage the automotive electronic explosion. The application of E/E system integration and modular assembly des...
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The author presents an overview on how an integrated E/E system designed for assembly and service can help manage the automotive electronic explosion. The application of E/E system integration and modular assembly design has been shown to effectively reduce the number of electronic modules and wiring harness circuits with which assembly and service must content. It is concluded that, in addition to reducing the number of boxes and wire, cost-effective assembly verification and service diagnostics can be achieved through E/E system integration when the particular requirements of assembly and service are understood and incorporated at design concept. The integrated E/E system can then transform the vehicle's E/E componentry from simply a 'passive recipient' to that of an 'active participant' within the assembly and service process.
A model is presented for predicting the cost of manufacturing printed wiring boards. The model represents manufacturing systems currently in use in the industry. The model concentrates on surface-mount technology, usi...
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A model is presented for predicting the cost of manufacturing printed wiring boards. The model represents manufacturing systems currently in use in the industry. The model concentrates on surface-mount technology, using a mixture of automatic, programmable-assembly and manual-assembly techniques. The model includes elements to account for inventory, assembly, and test and rework costs. The model also considers the effect of introducing a component type on total manufacturing cost.
VLSI/VHSIC technology poses critical test problems not only at the device level, but also at the system level. The extreme functional complexity and fail-operational redundancy of VLSI systems tends to render conventi...
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VLSI/VHSIC technology poses critical test problems not only at the device level, but also at the system level. The extreme functional complexity and fail-operational redundancy of VLSI systems tends to render conventional performance testing inadequate, not only in terms of failure mode coverage, but also in terms of test-time requirements. The authors propose a design structure in which various subsystems and modules using VLSI devices are related to one another in a hierarchical test scheme based on the reporting of individual, device-level built-in-test (BIT) results. This hierarchical approach offers true consistency between operational (in-flight), organizational, and depot-level test methodologies.
A description is given of the design of a broadband downconverter to cover both 4-GHz and 6-GHz common carrier bands. The downconverter was tested as a replacement for the downconverter in both the MDR-2204 and MDR-23...
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A description is given of the design of a broadband downconverter to cover both 4-GHz and 6-GHz common carrier bands. The downconverter was tested as a replacement for the downconverter in both the MDR-2204 and MDR-2306 4-GHz and 6-GHz radio systems, respectively. Excellent results have been observed in both radio systems. In threshold bit error rate (BER) tests, the downconverter provided 1.2-dB better performance than both radio systems. In overload BER tests, the downconverter showed a 0.5-dB better performance. The features credited for the good performance are: (1) the noise figure of the low-noise amplifier is less than 1.7 dB over the band;(2) the phase noise of the local oscillator is quite low;(3) the two-tone third-order intercept point of the downconverter is above 26 dBm;and (4) the image rejection is greater than 20 dB over the band.
Copper thick-film multilayer technology is evaluated for use as a high-frequency digital interconnect in systems with bit rates up to 600 Mb/s. To help design the interconnect, software tools which calculate the elect...
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Copper thick-film multilayer technology is evaluated for use as a high-frequency digital interconnect in systems with bit rates up to 600 Mb/s. To help design the interconnect, software tools which calculate the electrical parameters and performance for any two-dimensional geometry were developed and are described. The analysis is based on a quasistatic method. A thick-film multilayer test structure with high bandwidth and 50-Ω impedance was realized. The calculated line parameters show good agreement with the measured values.
Several methods of device and circuit modelling are reviewed, followed by a detailed outline of state-of-the-art equivalent circuit and physical modeling techniques applicable to both device and circuit design. It is ...
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Several methods of device and circuit modelling are reviewed, followed by a detailed outline of state-of-the-art equivalent circuit and physical modeling techniques applicable to both device and circuit design. It is noted that the requirement for CAD (computer-aided design) utilities which extend available linear design techniques into the large-signal regime is being met by both equivalent circuit and physical device models, coupled with powerful algorithms such as the harmonic balance technique. The advent of fast physical device models allows the designer to optimize both devices and circuits based on the actual device structure, without resorting to electrical measurements at the design stage. This is particularly important in the design of integrated circuits, where it is essential to minimize the cost of the design-fabrication cycle.< >
The author presents an algorithm for solving nonlinear equations obtained by coefficient matching. This synthesis method is very effective in continuous-time CMOS filter design. The advantages of the proposed method i...
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The author presents an algorithm for solving nonlinear equations obtained by coefficient matching. This synthesis method is very effective in continuous-time CMOS filter design. The advantages of the proposed method in comparison with the Newton method are shown. A procedure called SYNCOM has been written in Pascal to implement the algorithm.< >
Given a nonseparable plane graph G, a path or circuit is called dual if it is also a path or circuit, respectively, in the geometric dual of G. Motivated by a layout design problem of CMOS integrated circuits, the aut...
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Given a nonseparable plane graph G, a path or circuit is called dual if it is also a path or circuit, respectively, in the geometric dual of G. Motivated by a layout design problem of CMOS integrated circuits, the authors consider some problems of partitioning the edges of G into the minimum number of dual paths or circuits. The results include a constructive proof of the fact that the following problems are solvable in polynomial time: determining whether G has a dual circuit; finding a dual Eulerian path or circuit if one exists; and finding the minimum set of dual paths that partitions the edges of G when G has no dual circuits.< >
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