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FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond

FS2K: A Forksheet FET Technology Library and a Study of VLSI...

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ieee International symposium on circuits and systems (ISCAS)

作者： Yunjeong Shin Daehyeok Park Dohun Koh Dongryul Heo Jieun Park Hyundong Lee Jongbeom Kim Hyunsoo Lee Taigon Song School of Electronic and Electrical Engineering Kyungpook National University (KNU) Daegu South Korea School of Electronics Engineering Kyungpook National University (KNU) Daegu South Korea

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

The semiconductor foundries are now mass-producing 3nm transistors. In this trend, many studies on 2nm node report the potential of future transistors such as forksheet FET (FSFET) from the device perspective. However, only a few studies report the impact of advanced transistors at the full-chip level. Thus, this study focuses on enlightening the potential of FSFET at the full-chip level in the 2nm process compared to the 3nm node currently in mass production. To do this, we present FS2K, the first public 2nm technology library in FSFET, which provides the following results: 1) The simple scaling with no variation in devices or interconnect achieves only about 10% power reduction and area reduction in 2nm processes for FSFET and Nanoshet FET (NSFET). 2) An optimal performance improvement in a 2nm node requires FSFET to be designed in a 4T standard cell that is 1-track reduced from 3nm. Our 2nm 4T-FSFET design achieves -29.5% area reduction and -31.9% power reduction compared to the existing 3nm process. Thus, we emphasize the importance of optimization not only in the device but also in the cell layout for future processes.

关键词： Performance evaluation Process design Visualization Field effect transistors Layout Very large scale integration Libraries

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electronic design of an eight-channel-stimulator for DSP-driven cochlear prostheses and prospective rehabilitation technique dedicated to deafness disability

Electronic design of an eight-channel-stimulator for DSP-dri...

引用

ieee International symposium on Industrial electronics (ISIE)

作者： A.B. Hamida M. Masmoudi M. Ghorbel Dept. of Electr. Eng. Sfax Univ. Tunisia ENIS Electrical Engineering Department Enis Bpw University of Sfax-Tunisia Sfax Tunisia

ISBN: (纸本)0780366069

In this article, the authors were interested in the design of an electronic circuit for a versatile stimulator dedicated to cochlear prostheses. As a first approach, the design was tentatively conceived with eight stimulating channels because it could be possible to provide additional channels. On the other hand, a prospective technique for patient rehabilitation was also studied in order to test as well as to prove the efficiency and the versatility of the conceived stimulator. This under-the skin micro-stimulator is dedicated to operate with any DSP- driven cochlear-prosthesis systems for executing numerical data with great flexibility. The major parts in this electronic circuit were designed around a logical processing unit for commanding the stimulation stage. It includes a transmission bus, which could differentiate the two main stages: the decoding stage and the stimulation stage. When receiving transmitted data from the external processing part, the logic unit decodes information for commanding the eight stimulation channels. Channels work independently and were merely formed by CMOS-current sources delivering positive and negative stimuli. After processing sounds, appropriate numerical data would be transmitted from the external sound analyser to the internal micro-stimulator through an inductive link (radio-frequency communication link), using an amplitude-modulated carrier. Transmitted data specifies stimulation current level to generate at each specified channel as well as stimulation rhythm. The external processing permits sound energy extraction through different calculation methods. For rehabilitation, a visual aided-tool illustrated on computer screen was designed to identify extracted energies, and hence to control clinically stimulating-pulse levels. With this dedicated process, clinicians could set up therapeutic experiments during rehabilitation, adjust correctly the device operation-parameters and assess electrical charges (current-pulse level) i

关键词： electronic circuits Decoding Data mining Prosthetics Patient rehabilitation Circuit testing Skin Logic Radio frequency Rhythm

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Code Coverage Analysis using High-Level Decision Diagrams

Code Coverage Analysis using High-Level Decision Diagrams

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Jaan Raik Uljana Reinsalu Raimund Ubar Maksim Jenihhin Peeter Ellervee Department of Computer Engineering Tallinn University of Technology Tallinn Estonia

The paper proposes a novel method of analyzing code coverage metrics on a system representation called High-Level Decision Diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and test pattern generation. Current paper presents a technique, where fast HLDD based simulation is extended to support seamless code coverage analysis. We show how classical code coverage metrics can be directly mapped to HLDD constructs. In addition, we introduce an observability coverage calculation method using HLDD models. Experiments on ITC99 benchmark circuits indicate the feasibility of the proposed approach.

关键词： Analytical models Computational modeling Test pattern generators Observability Pattern analysis Computer simulation Integrated circuit measurements design engineering Software testing Process design

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An Approximate Method for The Fault Tolerance of SRAM-Based Near-Memory Multiply-Accumulate Units

An Approximate Method for The Fault Tolerance of SRAM-Based ...

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ieee International symposium on Intelligent Signal Processing and Communication systems (ISPACS)

作者： Yung-Chieh Lin Liang-Ying Su Shih-Hsu Huang Department of Electronic Engineering Chung Yuan Christian University Taoyuan Taiwan

ISBN: (数字)9798350389210

ISBN: (纸本)9798350389227

To address the von Neumann bottleneck, computing-in-memory is emerging as a prominent trend. While numerous studies have explored SRAM-based near-memory multiply-accumulate unit (MAC) design in recent years, they often overlook fault-tolerance techniques. In this paper, we propose integrating an approximate method into near-memory MAC circuits to prevent chips from becoming unusable due to a few faulty memory cells. If a memory cell responsible for calculating the most-significant-bit (MSB) fails, we reallocate the memory cell originally designated for calculating the least-significant-bit (LSB) to compute the MSB instead, thus minimizing computation errors. Experimental results demonstrate that the proposed approximate fault-tolerance mechanism incurs only a small additional area overhead but significantly reduces errors caused by memory cell faults.

关键词： Fault tolerance Communication systems Fault tolerant systems Signal processing In-memory computing Market research Circuit faults

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Application-aware LCA of semiconductors: Life-cycle energy of microprocessors from high-performance 32nm CPU to ultra-low-power 130nm MCU

Application-aware LCA of semiconductors: Life-cycle energy o...

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ieee International symposium on electronics and the Environment

作者： David Bol Sarah Boyd David Dornfeld ICTEAM Institute Université catholique de Louvain Louvain-la-Neuve Belgium Laboratory for Manufacturing and Sustainability University of California Berkeley USA

The exponential growth of the semiconductor industry raises serious environmental concerns. Accurate life-cycle data are critical for both appropriate product eco-design and life-cycle analysis (LCA) of new electronic applications. Previous semiconductor LCA efforts were based on generic studies dealing with an average component description such as microprocessors, DRAM or Flash memories without taking into account the broad application range of each component. In this paper, we show that accurate life-cycle data can only be obtained with an application-aware approach. We demonstrate this with a life-cycle energy evaluation of microprocessors for five different applications: from high-performance 32 nm CPUs for servers and laptops to low-power 45 nm processors for set-top boxes and smart phones to ultra-low-power 130 nm MCUs for wireless sensors. For each category, we model the energy of the CMOS processing steps for integrated circuit (IC) fabrication as well as the use phase energy demand including both active and stand-by modes. Results show that life-cycle energy varies by a factor 20000× between the high-performance and the ultra-low-power ends.

关键词： CMOS integrated circuits Servers Microprocessors Program processors Optical wavelength conversion Portable computers Smart phones

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A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead

A 2-port 6T SRAM bitcell design with multi-port capabilities...

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ieee International symposium on Quality electronic design

作者： Jawar Singh Dilip S. Aswar Saraju P. Mohanty Dhiraj K. Pradhan Department of Computer Science University of Bristol UK Department of Telecommunication Government of India New Delhi India Department of Computer Science and Engineering University of North Texas USA

ISBN: (纸本)9781424464548

Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we present a 2-port 6T SRAM bitcell with multi-port capabilities and a reduced area overhead compared to existing 2-port 7-transistor (7T) and 8T SRAM bitcells. The proposed 2-port bitcell has six transistors (6T) and single-ended read and write bitlines (RBL/WBL). We compare the stability, simultaneous read/write disturbance, SNM sensitivity and misread current from the read bitline with the 7T and 8T bitcells. The static noise margin (SNM) of the 6T bitcells around the write disturbed bitcell is 53% to 61% higher than that of the 7T bitcell. The average active power dissipation under the different read/write operations of the 6T bitcells is 28% lower than the 8T and equal to 7T bitcell. Hence, the proposed 2-port 6T-SRAM is a potential candidate in terms of process variability, stability, area, and power dissipation.

关键词： Random access memory Power dissipation Computer science Government SRAM chips Stability CMOS technology Process design circuits design engineering

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A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference

A Scalable RISC-V Vector Processor Enabling Efficient Multi-...

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ieee International symposium on circuits and systems (ISCAS)

作者： Chuanning Wang Chao Fang Xiao Wu Zhongfeng Wang Jun Lin School of Electronic Science and Engineering Nanjing University Nanjing China School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

RISC-V processors encounter substantial challenges in deploying multi-precision deep neural networks (DNNs) due to their restricted precision support, constrained throughput, and suboptimal dataflow design. To tackle these challenges, a scalable RISC-V vector (RVV) processor, namely SPEED, is proposed to enable efficient multi-precision DNN inference by innovations from customized instructions, hardware architecture, and dataflow mapping. Firstly, dedicated customized RISC-V instructions are proposed based on RVV extensions, providing SPEED with fine-grained control over processing precision ranging from 4 to 16 bits. Secondly, a parameterized multi-precision systolic array unit is incorporated within the scalable module to enhance parallel processing capability and data reuse opportunities. Finally, a mixed multi-precision dataflow strategy, compatible with different convolution kernels and data precision, is proposed to effectively improve data utilization and computational efficiency. We perform synthesis of SPEED in TSMC 28nm technology. The experimental results demonstrate that SPEED achieves a peak throughput of 287.41 GOPS and an energy efficiency of 1335.79 GOPS/W at 4-bit precision condition, respectively. Moreover, when compared to the pioneer open-source vector processor Ara, SPEED provides an area efficiency improvement of 2.04× and 1.63× under 16-bit and 8-bit precision conditions, respectively, which shows SPEED’s significant potential for efficient multi-precision DNN inference.

关键词： Program processors Convolution Artificial neural networks Parallel processing Throughput Vectors Distance measurement

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An Enhanced Computer Simulation Model of the ieee Std C62.41.2-2002 Surge Generator for Simulated Surge Testing of Electrical systems

An Enhanced Computer Simulation Model of the IEEE Std C62.41...

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ieee symposium on Product Compliance Engineering (PSES)

作者： Nosh K. Medora Alexander Kusko Exponent Failure Analysis Associates Inc. Phoenix AZ USA Exponent Failure Analysis Associates Inc. Natick MA USA

Computer modeling may be used to accurately model an ieee Std C62.41.2-2002 Combination Wave surge generator and apply the simulated surge waveform to a modeled system to determine the system's immunity to surge voltages. During the simulated surge tests, the designer can verify the suitability of the selected components, and, if necessary, judiciously perform a re-design at low cost and with little time expended. Furthermore, the designer can also observe the magnitude of the stresses imposed on the components by the simulated surge and thus determine the magnitude of the component voltages and currents, including dv/dt, di/dt, and the ringing frequency, thus allowing the designer to fully evaluate the adequacy, reliability and safety of the designed system. The authors evaluated a surge generator model published in an ieee paper in 2005 and determined that the model was inaccurate. Consequently, a new surge generator model was proposed. The novel features of this enhanced surge generator model are demonstrated for four different simulation runs, using an electronic circuit with an L-C input line filter. The four runs include two operating conditions: a) with a surge suppressor in the circuit and b) with the surge suppressor open- circuited. The connected load includes: 1) a motor load and 2) a resistive load.

关键词： Computer simulation Surges Computational modeling System testing Voltage circuits Performance evaluation Costs Stress Frequency

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A prototype modular detector design for high resolution positron emission mammography imaging

A prototype modular detector design for high resolution posi...

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ieee symposium on Nuclear Science (NSS/MIC)

作者： Nan Zhang C.J. Thompson D. Jolly F. Cayouette S. Kecani Biomedical Engineering Department McGill University Montreal QUE Canada Montreal Neurological Institute and the Biomedical Engineering Department McGill University Montreal QUE Canada Medical Cyclotron Facility of the MontrealNeurological Institute McGill University Montreal QUE Canada Machine shop of Physics Department McGill University Montreal QUE Canada

Current challenges facing us in developing dedicated position emission tomography (PET) system for metabolic breast mammography (PEM) and small animal (ANIPET) are to achieve high spatial resolution (less than 2 mm) and high efficiency. It is also crucial to extend the sensitive areas of PEM detectors to their periphery in order to overcome the difficulty in imaging near a patient's chest wall. This limitation of the periphery dead region was revealed in the clinical trials of our previously developed PEM-I systems. In the new study, we developed prototype detectors by using position-sensitive photomultiplier tubes (PS-PMTs) and pixelated bismuth germanate (BGO) crystals with depth encoding scheme to detect and localize gamma rays. The procedures in crystal processing include cutting, polishing, encapsulating, separating, and re-gluing. We also developed front-end electronic circuits including high-voltage dividers, anode resister chains, position readout circuits, and last dynode timing circuits. Methods for combining four PS-PMTs with simple X+, X-, Y+, Y- outputs have been developed to further simplify the position recording. The detectors were constructed in the structure of array (two in the system) - module (four in each array) - unit (four in each module). The basic unit of one crystal and one PS-PMT can be as field replaceable. Our new prototype detectors show that the proposed PEM-II system has a spatial resolution of 1.8 mm (vs. 2.8 mm in PEM-1), a timing resolution of 10.3 ns (vs. 12 ns in PEM-I), and a field-of-view of 88 mm /spl times/ 88 mm (vs. 64 mm x 56 mm in PEM-1). Compared with our previous PEM-I system, it demonstrates that the design improves the spatial resolution, enhances the detector field-of-view, and significantly reduces the peripheral dead regions.

关键词： Prototypes Image resolution Radioactive decay Mammography High-resolution imaging Spatial resolution Gamma ray detection Gamma ray detectors Position sensitive particle detectors circuits

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Web-Based Framework for Parallel Distributed Test

Web-Based Framework for Parallel Distributed Test

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11th International Workshop on design and diagnostics of electronic circuits and systems (DDECS)

作者： Eero Ivask Jaan Raik Raimund Ubar Tallinn University of Technology Tallinn Estonia

In this paper we describe web-based distributed system suitable for acceleration of fault simulation in digital circuits. Framework has three-tier client server concept. Java applets are used for user interfaces. Java servlet on master server supports communication, task partitioning, user tracking, data management, etc. HTTP protocol based solution is used, since it is well established and flexible in firewall-protected environments. Reuse of existing test tools by encapsulation into Java agents extends the lifecycle and value of these tools. Considerable fault simulation speedup was gained in experiments. Two types of fault set partitioning were tried: adjacent fault selection and random fault selection. The latter is able to ensure more equal execution times for subtasks and therefore contributes to overall shorter parallel simulation time.

关键词： Circuit faults Java Circuit testing Web server Acceleration Circuit simulation Digital circuits User interfaces Protocols Protection

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