Successful design of digital systems without a common clock signal necessitates careful timing control. This requires understanding and quantitative characterization of flip-flop behavior under metastable operation. A...
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Successful design of digital systems without a common clock signal necessitates careful timing control. This requires understanding and quantitative characterization of flip-flop behavior under metastable operation. A general method of CMOS RS flip-flop design with minimum probability of timing errors due to metastable operation is presented. The key to the method is the proper choice of the NMOS and PMOS transistor dimensions to attain the minimal resolving time from a metastable state. An analytical formula for the flip-flop time constant parameter of resolution from metastable state was derived using the Shichman-Hodges model for MOSFETs, including parasitic capacitances of the circuit layout. The method assumes n-well technology;it can be extended to designs made in other CMOS technologies.
A computer model has been developed for simulating N-conductor transmission lines terminated with nonlinear complex loads. A modal analysis is used to describe incident and refected waves on the transmission lines. Th...
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A computer model has been developed for simulating N-conductor transmission lines terminated with nonlinear complex loads. A modal analysis is used to describe incident and refected waves on the transmission lines. The loads are modeled as parallel R-C networks with a voltage dependent resistance and source. For each load a matrix differential equation is written for the unknown load voltage due to some incident voltage. The matrix equation is solved numerically using a first-order finite difference approximation.
A technique for the study of mutually synchronized fault-tolerant clock systems is introduced. Present understanding is only marginal due to their hybrid (analog/digital) nature and also due to their inherently comple...
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ISBN:
(纸本)0818607033
A technique for the study of mutually synchronized fault-tolerant clock systems is introduced. Present understanding is only marginal due to their hybrid (analog/digital) nature and also due to their inherently complex mutual feedback structure. Their design and performance evaluation in the presence of single and multiple-module failures is the object of this study. It is demonstrated through the actual design and implementation of two prototypes, that a combination of simulation and analysis of their constituent units, using a judicious mix of time-amplitude and time-phase domain representations, constitutes an indispensable design tool and a very important aid to obtaining high-performance hardware implementations. The problem of clique formations under multiple-module fault conditions was reexamined and a practical solution that was experimentally verified is presented.
The authors describe a new method of pseudoexhaustive test pattern generation for switching circuits with structured design. Two linear feedback shift registers (LFSR) are used to generate the scan address and the tes...
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ISBN:
(纸本)0818607033
The authors describe a new method of pseudoexhaustive test pattern generation for switching circuits with structured design. Two linear feedback shift registers (LFSR) are used to generate the scan address and the test pattern to be scanned into this address. The m-bit LFSR for test pattern generation produces code words of a cyclic (2**m- 1,m) code which are used as test patterns for combinational circuits. After the exhaustion of all code words the sequence of scan addresses is changed, which has the effect of permuting the code bits. The probability of exhaustive testing of a combinational r-input circuit is determined for r less than equivalent to m, whereas for r less than m the relative coverage is introduced. The probabilistic evaluation of test effectiveness is compared with the simulation results. It is shown that the suggested permutation of test bits gives better results than random testing. The test pattern generation method is well suited for circuitsdesigned with the random-access scan (RAS) method, but it can be used in connection with other scan design methods as well.
The modeling, design and implementation of monolithic distributed RC networks for the MOS technology are described. The proposed design method guarantees a fast, and process-insensitive layout and the maximum yield wi...
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The modeling, design and implementation of monolithic distributed RC networks for the MOS technology are described. The proposed design method guarantees a fast, and process-insensitive layout and the maximum yield within a given process window. The procedure is demonstrated on an anti-aliasing/smoothing low-pass filter used in PCM channel bank filters.
The authors describe a new logic synthesis system for interactive and hierarchical VLSI logic design. This system, called FOX, allows designers to build circuits with functional level entities (register, decoder,. . ....
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The authors describe a new logic synthesis system for interactive and hierarchical VLSI logic design. This system, called FOX, allows designers to build circuits with functional level entities (register, decoder,. . . ), and can synthesize the optimized gate-level circuits that depend on target VLSI technology. FOX can also supply an interactive hierarchical design environment for logic designers. FOX has been used to designelectronic switching systems and processors, among many others.
The authors present a systematic study of the generation, classification and design of stray-insensitive single operational-amplifier (OA) switched-capacitor (SC) networks. The method leads to general structures witho...
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The authors present a systematic study of the generation, classification and design of stray-insensitive single operational-amplifier (OA) switched-capacitor (SC) networks. The method leads to general structures without redundant elements. The complete set of networks is then separated in two major classes. For each class all realizable transfer functions are determined, as well as the best ways to implement them. A design example is presented. The new circuits obtained compare favorably with previously reported realizations.
A versatile phase-compensated inverting integrator circuit is presented. The circuit, which uses two op-amps, is versatile in the sense that, unlike existing compensated integrators, it provides compensation at each o...
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A versatile phase-compensated inverting integrator circuit is presented. The circuit, which uses two op-amps, is versatile in the sense that, unlike existing compensated integrators, it provides compensation at each op-amp output. Hence, different designs for the same circuit are possible. The design and some applications of the circuit are discussed. The circuit is also designed to correct phase errors in the well-known Tow-Thomas and KHN biquads. Experimental results are found to be in good agreement with the theory.
Several novel, fully differential switched-capacitor all-pass biquad topologies are presented. These topologies, besides offering the well-known noise immunity properties of fully differential circuits, are shown to r...
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Several novel, fully differential switched-capacitor all-pass biquad topologies are presented. These topologies, besides offering the well-known noise immunity properties of fully differential circuits, are shown to require relatively little capacitor area for the realization of higher-Q circuits and to possess superior sensitivity properties. In addition, the new topologies can be readily staggered in a multibiquad filter so that errors due to op amp setting can be minimized. The design techniques used can be extended to all classes of biquadratic notch circuits. Monte Carlo simulations demonstrate the merit of the new circuits.
A direct and analytic method is presented for the design of a diplexer having a Butterworth characteristic at zero and infinite frequencies and any desired insertion loss at crossover frequency. It is shown that a thr...
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A direct and analytic method is presented for the design of a diplexer having a Butterworth characteristic at zero and infinite frequencies and any desired insertion loss at crossover frequency. It is shown that a three-port network exists if and only if the numerator and denominator polynomials of Z//1 (s) and Z//2 (s) are strictly Hurwitz with positive coefficients. Then the problem reduces to that of obtaining a better response using higher order polynomials. In the solution process, the elements of the scattering matrix are determined by solving the unknown coefficients of the numerator and denominator polynomials of input impedances Z//1 (s) and Z//2 (s). This transformation makes the problem solvable.
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