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A complete node for power line communications in a single chip

A complete node for power line communications in a single ch...

引用

ieee International symposium on Power Line Communications and Its Applications (ISPLC)

作者： A. Sanz J.I. Garcia-Nicolas P. Estopinan Department of Electronic Engineering CPS University of Zaragoza Zaragoza Spain Advanced Digital Design S.A. CEEI Aragon Zaragoza Spain

This paper describes the implementation of a complete node for narrow band power line communications (PLC) in a new single chip. This chip, named ADD1000, includes an 8051 microcontroller, a 14 bit enhanced UART designed for the medium access control (MAC) tasks and a modem circuit for PLC. This work is based in previous designs (A. Sanz et al., 2001) (J.I. Garcia Nicolas et al., 2000) but introduces some key improvements. Low power modes, and other upgrades, are built in the micro-controller. Also, the MAC is modified in order to support, not only the European Home systems specifications (EHS) for the power line medium (1997), but also KONNEX (KNX) (2000), IEC 61334, HTTP and TCP/IP. The PLC modem is changed to use band pass converters. Finally a software layer has been developed to support the HTTP and TCP/IP using the MAC and modem of chip. Using this soft layer any device using the ADD1000 chip can be an embedded Web server of a TCP/IP PLC network.

关键词： Power line communications Programmable control Modems TCPIP Narrowband Microcontrollers Media Access Protocol circuits IEC standards Web server

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design OF RELIABLE INTERFACE SYSTEM FOR EDDY CURRENT DISPLACEMENT SENSORS IN VACUUM ENVIRONMENTS

DESIGN OF RELIABLE INTERFACE SYSTEM FOR EDDY CURRENT DISPLAC...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.6

作者： Mohammad Reza Nabavi Stoyan Nihtianov Electronic Instrumentation Laboratory Delft University of Technnology Netherlands

In this paper we propose a reliable interface concept for eddy current displacement sensors. The implementation of a signal conditioning approach, based on simple electronic circuits, is also discussed. The interface system is designed for medium to high-resolution applications in the sub-micron displacement measurement range. The application of the sensor is in special vacuum environment with severe restrictions of power dissipation, and increased requirements for reliability and thermal drift. The new system is expected to consume less than 20 mW, and to have a very low thermal drift. The implementation will be a system-in-package (SIP). The full-scale range of the measured displacement is 1 mm with 50 KHz signal bandwidth and 11 bits resolution (less than 500 nm). The signal conditioning interface is utilizing a standard 0.35 (mu)m CMOS technology. The discussions are based on simulations and primary experimental results, promising a proper sensor operation.

关键词： eddy current displacement low-power low-thermal drift interface

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Super abacus: a Beowulf class parallel computer for multimedia signal processing research

Super abacus: a Beowulf class parallel computer for multimed...

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International symposium on Intelligent Multimedia, Video and Speech Processing

作者： Lai-Man Po Chun-Ho Cheung Ka-Man Wong CityU Image Processing Laboratory Department of Electronic Engineering City University of Hong Kong Hong Kong China

ISBN: (纸本)9628576623

A few thousands years ago, Chinese people used small rods connected to movable counters such as beads to construct a low-cost calculation device, which is called Abacus. Today, Beowulf-class parallel computer using such similar approach to construct a low-cost supercomputing system, in which Pentium-based computers (beads) are connected by a Fast Ethernet switch (rods) to form a parallel supercomputer. This paper presents our experiences learnt from the construction of a 17-node Beowulf-class cluster called Super Abacus. The system is designed to provide high computational power for handling real-time multimedia signal processing such as audio/video compression, multimedia database searching and content-based audio/video classification so as to support multimedia signal processing research projects in CityU Image Processing Laboratory. The technologies and methodologies to achieve the goal of lower system cost with better performance will be described.

关键词： Concurrent computing Multimedia databases Switches Multimedia systems Video signal processing Video compression Counting circuits Ethernet networks Supercomputers Signal design

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Power Integrity Concepts for High-Speed design on Multi-Layer PCBs - (PPT)

Power Integrity Concepts for High-Speed Design on Multi-Laye...

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ieee symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity

作者： Chulsoon Hwang Missouri EMC Laboratory

PWR/GND plane pair nearer to the IC in stackup will minimize L_(PCB_IC) from package balls to power net area fill (smaller loop). PWR/GND plane pairs closely spaced will reduce L_(PCB_plane).

ISBN: (纸本)9781538666227

PWR/GND plane pair nearer to the IC in stackup will minimize L_(PCB_IC) from package balls to power net area fill (smaller loop). PWR/GND plane pairs closely spaced will reduce L_(PCB_plane).

关键词： Integrated circuits Capacitors Physics Pins Power systems Jitter Geometry PIN Bone Nails Jitter power systems Capacitors geometry Physics Integrated circuits electronic circuits slump Polychlorinated Biphenyls

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Solar Intensity X-Ray Spectrometer (SIXS) ASIC for a large dynamic range onboard BepiColombo ESA mission to Mercury

Solar Intensity X-Ray Spectrometer (SIXS) ASIC for a large d...

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2007 ieee Nuclear Science symposium Conference (NSS 2007), vol.3

作者： Farah F. Khalid Mark L. Prydderch Quentin Morrissey Paul Seller Eino Valtonen Juhani Peltonen Matti Anttila Anssi Malkki Rami Vainio Juhani Huovelin STFC Rutherford Appleton Laboratory Oxfordshire UK Department of Physics Turku University Finland Aboa Space Research Oy Turku Finland Space Systems Finland Limited Espoo Finland Space Research Finnish Meteorological Institute Helsinki Finland Department of Physical Sciences University of Helsinki Finland The Observatory University of Helsinki Finland

The SIXS instrument is designed for detecting and measuring solar X-rays and solar energetic particles in a Mercury orbit onboard BepiColombo. The particle detector consists of a CsI(TI) core detector and 5 GaAs surface detectors. The front-end electronics of the particle detector is implemented as an ASIC which requires a large dynamic range of 2,000e- to 1,500,000e- and an integral non-linearity (INL) <3% for a temperature range of -30℃ to +55℃. The SIXS ASIC test structure has been manufactured to determine performance of differential vs. single-ended designs for noise, power supply rejection and current consumption. The ASIC has 8 channels, each of which consists of a preamplifier, a CR-RC shaper, a peak hold, a comparator and a buffer, all designed using enclosed geometry transistors. There are 6 channels for GaAs detectors with 3 different preamplifier types consisting of a single-ended with pole zero compensation;single-ended without pole zero compensation and a differential configuration. There are 2 channels for CsI detectors with single-ended and differential preamplifier designs. This ASIC has been manufactured in a 0.35μm CMOS process. The ASIC architecture and design flow are described including simulated and measured results.

关键词： Spectroscopy Application specific integrated circuits Dynamic range Preamplifiers Extraterrestrial measurements Radiation detectors Gallium arsenide electronic equipment testing Poles and zeros Instruments

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Linear-enhanced V to I converters based on MOS resistive source degeneration

Linear-enhanced V to I converters based on MOS resistive sou...

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2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.9

作者： Belen Calvo Antonio J. Lopez-Martin Sandhana Balasubramanian Jaime Ramirez-Angulo Ramon G. Carvajal Group of Electronic Design University of Zaragoza Zaragoza Spain Klipsch School of Electrical and Computer Engineering New Mexico State University Las Cruces NM USA Department Electrical and Electronic Eng Public University of Navarra Pamplona Spain Escuela Superior de Ingenieros University of Seville Seville Spain

This paper describes the application of the quasi-floating gate technique to overcome the common mode sensitivity of the degeneration MOS resistors, which results in a significant linearity improvement and an enhanced CMRR. The proposed approach requires minimal additional hardware, does not require increased supply voltages or additional quiescent power dissipation and preserves the possibility of tuning the MOS resistor value through small gate voltage variations. Results from two different linearized MOS source degeneration schemes implemented in a 0.5(mu)m CMOS technology verify the feasibility of the presented solution.

关键词： Voltage Resistors Linearity CMOS technology Power dissipation Hardware MOSFET circuits Circuit optimization design engineering Application software

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Processor based Intrinsic PUF design for Approximate Computing: Faith or Reality?

Processor based Intrinsic PUF Design for Approximate Computi...

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ieee Asian Hardware-Oriented Security and Trust (AsianHOST)

作者： Aditya Japa Jiliang Zhang Weiqiang Liu Chongyan Gu Centre for Secure Information Technologies (CSIT) ECIT Queen’s University Belfast Belfast U.K. College of Semiconductors (College of Integrated Circuits) Hunan University Changsha China College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics Nanjing China

Approximate computing has recently emerged as an advanced computing paradigm for energy efficient and lightweight system design. However, several potential vulnerabilities and threats show a negative impact on the security and integrity of approximate computing systems. To address this, a processor datapath based intrinsic PUF design methodology is demonstrated for approximate computing. This work investigates and verifies the effectiveness of processor based PUF design for approximate computing. First, an 8-bit ripple carry adder is analyzed by applying a popular approximate computing technique namely voltage over-scaling. Due to the voltage over-scaling and process variations, the ripple carry adder shows stochastic timing errors. Exploiting this phenomenon, CMOS based datapath is designed and operated in approximate computing region to generate PUF response. It is observed that with the reduction in supply voltage, harvested PUF bits show increased uniqueness. At a 45nm technology node and 0.5V supply voltage, the extracted PUF bits exhibit a maximum uniqueness of 40.31%. Moreover, the reliability of PUF reduces with scaling supply voltage, exhibiting a reliability of 85.67 (at 0.5V) with a temperature range of −30°C to 80°C. Interestingly, the uniqueness of PUF bits increases with the reduction in power consumption of datapath for approximate computing. Thus, designing intrinsic processor based PUFs shows large benefits and scope due to the increased vulnerabilities and lower resource utilization of approximate computing.

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A Multi-Level Phase Detector in 90 nm CMOS

A Multi-Level Phase Detector in 90 nm CMOS

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ieee Latin American symposium on circuits and systems

作者： C. Sanchez-Azqueta S. Celma C. Gimeno Group of Electronic Design University of Zaragoza

ISBN: (纸本)9781467312073

This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing seven levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang phase detectors, a scheme of phase delay sensing is proposed that eliminates the need to sample the data stream close to data transitions in the locked state. Behavioural simulations of the proposed phase detector are provided, as well as of its performance in a CDR circuit.

关键词： Phase detectors clock and data recovery circuits Metastable state

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A High-Speed Variable Phase Accumulator for an ADPLL Architecture

A High-Speed Variable Phase Accumulator for an ADPLL Archite...

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2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.5

作者： Liangge Xu Saska Lindfors Electronic Circuit Design Laboratory Helsinki University of Technology Finland

This paper presents a high-speed topology for the variable phase accumulator (VPA) in an all digital phase-locked loop (ADPLL) architecture. The topology increases the speed of the VPA, which is a digital block running at the highest frequency in the ADPLL. The high-speed feature of the topology is achieved by exploiting the fact that the VPA output is used in the reference frequency domain while the circuit needs to handle the RF signal from the ADPLL output. The new topology minimizes the timing critical path and reduces the logic in the highest frequency domain to a shift register. As demonstrated in a 65-nm CMOS process, it allows the VPA to have a speed increase of about 60percent without penalty in power dissipation or silicon area.

关键词： Circuit topology Radio frequency Digital integrated circuits Frequency synthesizers Phase locked loops Frequency domain analysis Radiofrequency integrated circuits Circuit synthesis Timing Silicon

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Antenna Arrays Calibration Using Recursive Least Squares Adaptive Filtering Algorithms Based on Inverse QR Decomposition

Antenna Arrays Calibration Using Recursive Least Squares Ada...

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East-West design & Test symposium (EWDTS)

作者： Victor Djigan Vladislav Kurganov Department of Integrated Circuits Design Methodology Institute for Design Problems in Microelectronics of RAS Moscow Russia Institute of Microdevices and Control Systems National Research University of Electronic Technology Moscow Russia

ISBN: (数字)9781728198996

ISBN: (纸本)9781728199009

This paper considers the antenna arrays calibration by the using of the Recursive Least Squares (RLS) adaptive filtering algorithms. An algorithm, based on the inverse QR decomposition, has been selected among the diversity of the RLS algorithms. This is caused by its stable operation. Because the algorithm contains the computationally heavy square root operations, a square root free version of the algorithm is also presented. Both versions of the QR RLS algorithms are mathematically identical to each other if they operate in float point arithmetic. The proposed calibration can be used in the antenna arrays with digital beamforming, because the algorithms usage requires the access to the array channel signals. The calibration requires a known training signal, which can be easily provided not only in a laboratory environment, but also in a field operation, if an array is used as a directional antenna of the digital communication system equipment. In the second case, the calibration can be also conducted even in the presence of the interference signal sources. Simulation validates the proposed calibration algorithm, using linear antenna arrays with 4, 8 and 16 antennas with a half wavelength distance between the neighbor antennas. In this simulation, the array channel noise has been varied in 0 ... 30 dB range of the Signal-to-Noise Ratio. Two interference sources with the -30 dB Signal-to-Interference Ratio each have been simulated. These sources were located symmetrically relatively the required main lobe direction of the array radiation pattern. A training signal has been simulated as a random one with no specific autocorrelation properties. The signal has been modulated by the Phase Shift Keying (PSK) and the Quadrature Amplitude Modulation.

关键词： Calibration Interference Filtering algorithms Signal processing algorithms Matrix decomposition Correlation Array signal processing

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