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The ALICE TPC front end electronics

The ALICE TPC front end electronics

引用

ieee symposium on Nuclear Science (NSS/MIC)

作者： L. Musa J. Baechler N. Bialas R. Bramm R. Campagnolo C. Engster F. Formenti U. Bonnes R. Esteve Bosch U. Frankenfeld P. Glassel C. Gonzales H.-A. Gustafsson A. Jimenez A. Junique J. Lien V. Lindenstruth B. Mota P. Braun-Munzinger H. Oeschler L. Osterman R. Renfordt G. Ruschmann D. Rohrich H.-R. Schmidt J. Stachel A.-K. Soltveit K. Ullaland CERN Geneva Switzerland Institute für Kemphysik Johann-Wolfgang-Universitat Frankfurt Germany Institut für Kernphysik Technische Universität Darmstadt Germany GSI Darmstadt Germany Physikalisches Institut Ruprecht-Karls-Universität Heidelberg Germany Division of High Energy Physics University of Lund Sweden University of Bergen Bergen Norway Kirchhoff_ Institut für Physik Ruprecht-Karls-Universität Heidelberg Germany

In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS). A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the system meets all design requirements. Originally conceived and optimized for the time projection chamber (TPC) of the ALICE experiment, its architecture and programmability make this system suitable for the readout of a wider class of detectors.

关键词： Control systems Application specific integrated circuits Detectors Data acquisition electronic equipment testing Tail Filters Cables Distributed control Prototypes

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A Novel Multiscroll Chaotic System and Its Realization

A Novel Multiscroll Chaotic System and Its Realization

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.7

作者： Simin Yu Jinhu Lu Guanrong Chen College of Automation Guangdong University of Technology Guangzhou China Academy of Mathematics and Systems Science Chinese Academy and Sciences Beijing China Department of Electronic Engineering City University of Hong Kong Hong Kong China

This paper proposes a novel multiscroll chaotic system, which is different from Chua's circuit and all its variants in most aspects of the algebraic form, circuit design, and geometrical structure of the attractor. In particular, the multiscroll attractor of this new system is more complex than that of the generalized Chua's circuit when they both have the same number of scrolls. The dynamical behaviors of the new system are then analyzed, including the bifurcation diagram and the Lyapunov exponent spectra. Moreover, a module-based circuit diagram is designed for realizing various multiscroll attractors. Finally, experimental circuits are implemented with physical observations reported.

关键词： Chaos Circuit synthesis Nonlinear circuits Educational institutions design automation design engineering Mathematics Bifurcation Hysteresis Capacitors

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Power Integrity Concepts for High-Speed design on Multi-Layer PCBs - (PPT)

Power Integrity Concepts for High-Speed Design on Multi-Laye...

引用

ieee symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity

作者： Chulsoon Hwang Missouri EMC Laboratory

PWR/GND plane pair nearer to the IC in stackup will minimize L_(PCB_IC) from package balls to power net area fill (smaller loop). PWR/GND plane pairs closely spaced will reduce L_(PCB_plane).

ISBN: (纸本)9781538666227

PWR/GND plane pair nearer to the IC in stackup will minimize L_(PCB_IC) from package balls to power net area fill (smaller loop). PWR/GND plane pairs closely spaced will reduce L_(PCB_plane).

关键词： Integrated circuits Capacitors Physics Pins Power systems Jitter Geometry PIN Bone Nails Jitter power systems Capacitors geometry Physics Integrated circuits electronic circuits slump Polychlorinated Biphenyls

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Linear-enhanced V to I converters based on MOS resistive source degeneration

Linear-enhanced V to I converters based on MOS resistive sou...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.9

作者： Belen Calvo Antonio J. Lopez-Martin Sandhana Balasubramanian Jaime Ramirez-Angulo Ramon G. Carvajal Group of Electronic Design University of Zaragoza Zaragoza Spain Klipsch School of Electrical and Computer Engineering New Mexico State University Las Cruces NM USA Department Electrical and Electronic Eng Public University of Navarra Pamplona Spain Escuela Superior de Ingenieros University of Seville Seville Spain

This paper describes the application of the quasi-floating gate technique to overcome the common mode sensitivity of the degeneration MOS resistors, which results in a significant linearity improvement and an enhanced CMRR. The proposed approach requires minimal additional hardware, does not require increased supply voltages or additional quiescent power dissipation and preserves the possibility of tuning the MOS resistor value through small gate voltage variations. Results from two different linearized MOS source degeneration schemes implemented in a 0.5(mu)m CMOS technology verify the feasibility of the presented solution.

关键词： Voltage Resistors Linearity CMOS technology Power dissipation Hardware MOSFET circuits Circuit optimization design engineering Application software

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design OF RELIABLE INTERFACE SYSTEM FOR EDDY CURRENT DISPLACEMENT SENSORS IN VACUUM ENVIRONMENTS

DESIGN OF RELIABLE INTERFACE SYSTEM FOR EDDY CURRENT DISPLAC...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.6

作者： Mohammad Reza Nabavi Stoyan Nihtianov Electronic Instrumentation Laboratory Delft University of Technnology Netherlands

In this paper we propose a reliable interface concept for eddy current displacement sensors. The implementation of a signal conditioning approach, based on simple electronic circuits, is also discussed. The interface system is designed for medium to high-resolution applications in the sub-micron displacement measurement range. The application of the sensor is in special vacuum environment with severe restrictions of power dissipation, and increased requirements for reliability and thermal drift. The new system is expected to consume less than 20 mW, and to have a very low thermal drift. The implementation will be a system-in-package (SIP). The full-scale range of the measured displacement is 1 mm with 50 KHz signal bandwidth and 11 bits resolution (less than 500 nm). The signal conditioning interface is utilizing a standard 0.35 (mu)m CMOS technology. The discussions are based on simulations and primary experimental results, promising a proper sensor operation.

关键词： eddy current displacement low-power low-thermal drift interface

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Processor based Intrinsic PUF design for Approximate Computing: Faith or Reality?

Processor based Intrinsic PUF Design for Approximate Computi...

引用

ieee Asian Hardware-Oriented Security and Trust (AsianHOST)

作者： Aditya Japa Jiliang Zhang Weiqiang Liu Chongyan Gu Centre for Secure Information Technologies (CSIT) ECIT Queen’s University Belfast Belfast U.K. College of Semiconductors (College of Integrated Circuits) Hunan University Changsha China College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics Nanjing China

Approximate computing has recently emerged as an advanced computing paradigm for energy efficient and lightweight system design. However, several potential vulnerabilities and threats show a negative impact on the security and integrity of approximate computing systems. To address this, a processor datapath based intrinsic PUF design methodology is demonstrated for approximate computing. This work investigates and verifies the effectiveness of processor based PUF design for approximate computing. First, an 8-bit ripple carry adder is analyzed by applying a popular approximate computing technique namely voltage over-scaling. Due to the voltage over-scaling and process variations, the ripple carry adder shows stochastic timing errors. Exploiting this phenomenon, CMOS based datapath is designed and operated in approximate computing region to generate PUF response. It is observed that with the reduction in supply voltage, harvested PUF bits show increased uniqueness. At a 45nm technology node and 0.5V supply voltage, the extracted PUF bits exhibit a maximum uniqueness of 40.31%. Moreover, the reliability of PUF reduces with scaling supply voltage, exhibiting a reliability of 85.67 (at 0.5V) with a temperature range of −30°C to 80°C. Interestingly, the uniqueness of PUF bits increases with the reduction in power consumption of datapath for approximate computing. Thus, designing intrinsic processor based PUFs shows large benefits and scope due to the increased vulnerabilities and lower resource utilization of approximate computing.

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A complete node for power line communications in a single chip

A complete node for power line communications in a single ch...

引用

ieee International symposium on Power Line Communications and Its Applications (ISPLC)

作者： A. Sanz J.I. Garcia-Nicolas P. Estopinan Department of Electronic Engineering CPS University of Zaragoza Zaragoza Spain Advanced Digital Design S.A. CEEI Aragon Zaragoza Spain

This paper describes the implementation of a complete node for narrow band power line communications (PLC) in a new single chip. This chip, named ADD1000, includes an 8051 microcontroller, a 14 bit enhanced UART designed for the medium access control (MAC) tasks and a modem circuit for PLC. This work is based in previous designs (A. Sanz et al., 2001) (J.I. Garcia Nicolas et al., 2000) but introduces some key improvements. Low power modes, and other upgrades, are built in the micro-controller. Also, the MAC is modified in order to support, not only the European Home systems specifications (EHS) for the power line medium (1997), but also KONNEX (KNX) (2000), IEC 61334, HTTP and TCP/IP. The PLC modem is changed to use band pass converters. Finally a software layer has been developed to support the HTTP and TCP/IP using the MAC and modem of chip. Using this soft layer any device using the ADD1000 chip can be an embedded Web server of a TCP/IP PLC network.

关键词： Power line communications Programmable control Modems TCPIP Narrowband Microcontrollers Media Access Protocol circuits IEC standards Web server

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A Multi-Level Phase Detector in 90 nm CMOS

A Multi-Level Phase Detector in 90 nm CMOS

引用

ieee Latin American symposium on circuits and systems

作者： C. Sanchez-Azqueta S. Celma C. Gimeno Group of Electronic Design University of Zaragoza

ISBN: (纸本)9781467312073

This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing seven levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang phase detectors, a scheme of phase delay sensing is proposed that eliminates the need to sample the data stream close to data transitions in the locked state. Behavioural simulations of the proposed phase detector are provided, as well as of its performance in a CDR circuit.

关键词： Phase detectors clock and data recovery circuits Metastable state

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Solar Intensity X-Ray Spectrometer (SIXS) ASIC for a large dynamic range onboard BepiColombo ESA mission to Mercury

Solar Intensity X-Ray Spectrometer (SIXS) ASIC for a large d...

引用

2007 ieee Nuclear Science symposium Conference (NSS 2007), vol.3

作者： Farah F. Khalid Mark L. Prydderch Quentin Morrissey Paul Seller Eino Valtonen Juhani Peltonen Matti Anttila Anssi Malkki Rami Vainio Juhani Huovelin STFC Rutherford Appleton Laboratory Oxfordshire UK Department of Physics Turku University Finland Aboa Space Research Oy Turku Finland Space Systems Finland Limited Espoo Finland Space Research Finnish Meteorological Institute Helsinki Finland Department of Physical Sciences University of Helsinki Finland The Observatory University of Helsinki Finland

The SIXS instrument is designed for detecting and measuring solar X-rays and solar energetic particles in a Mercury orbit onboard BepiColombo. The particle detector consists of a CsI(TI) core detector and 5 GaAs surface detectors. The front-end electronics of the particle detector is implemented as an ASIC which requires a large dynamic range of 2,000e- to 1,500,000e- and an integral non-linearity (INL) <3% for a temperature range of -30℃ to +55℃. The SIXS ASIC test structure has been manufactured to determine performance of differential vs. single-ended designs for noise, power supply rejection and current consumption. The ASIC has 8 channels, each of which consists of a preamplifier, a CR-RC shaper, a peak hold, a comparator and a buffer, all designed using enclosed geometry transistors. There are 6 channels for GaAs detectors with 3 different preamplifier types consisting of a single-ended with pole zero compensation;single-ended without pole zero compensation and a differential configuration. There are 2 channels for CsI detectors with single-ended and differential preamplifier designs. This ASIC has been manufactured in a 0.35μm CMOS process. The ASIC architecture and design flow are described including simulated and measured results.

关键词： Spectroscopy Application specific integrated circuits Dynamic range Preamplifiers Extraterrestrial measurements Radiation detectors Gallium arsenide electronic equipment testing Poles and zeros Instruments

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Terahertz Planar Dual-Polarization Quadrature Mixer for Fiber-THz-Fiber High-Speed Wireless Link (invited paper)

Terahertz Planar Dual-Polarization Quadrature Mixer for Fibe...

引用

ieee International Workshop on Radio-Frequency Integration Technology (RFIT)

作者： Yang Liu Xiang Wu Hao Jiang Fan Yang Feiliang Chen Mo Li Jian Zhang University of Electronic Science and Technology of China Chengdu China

ISBN: (数字)9798331541095

ISBN: (纸本)9798331541101

Polarization multiplexing technology has the advantages of double data rate and bidirectional communication, which is an effective way to improve the channel capacity and spectrum utilization of communication systems in the future. However, the existing THz polarization multiplexing front-end circuits are faced with the key problems such as poor isolation, unbalance of amplitude and phase and difficult planar integration. In this paper, a novel and compact architecture of planar integrated dual-polarization quadrature mixer is proposed, focusing on the design of THz amplitude-phase balanced quadrature mixers. Based on anti-parallel Schottky diodes, a quadrature subharmonic mixer in the 330 GHz band has been designed. Measurement results show that, the single sideband conversion loss is 10.5-13.5 dB in the range of 310-348 GHz, and the image rejection ratio is basically better than 15 dB. The THz quadrature mixer proposed in this paper can be used as an optical fiber extender or THz wireless bridge to establish high-speed wireless links in areas where optical fibers are difficult or expensive to lay out.

关键词： Wireless communication Radio frequency Optical fiber polarization Multiplexing Schottky diodes Transceivers Optical fiber communication Loss measurement Mixers Terahertz communications

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