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Terahertz Planar Dual-Polarization Quadrature Mixer for Fiber-THz-Fiber High-Speed Wireless Link (invited paper)

Terahertz Planar Dual-Polarization Quadrature Mixer for Fibe...

引用

ieee International Workshop on Radio-Frequency Integration Technology (RFIT)

作者： Yang Liu Xiang Wu Hao Jiang Fan Yang Feiliang Chen Mo Li Jian Zhang University of Electronic Science and Technology of China Chengdu China

ISBN: (数字)9798331541095

ISBN: (纸本)9798331541101

Polarization multiplexing technology has the advantages of double data rate and bidirectional communication, which is an effective way to improve the channel capacity and spectrum utilization of communication systems in the future. However, the existing THz polarization multiplexing front-end circuits are faced with the key problems such as poor isolation, unbalance of amplitude and phase and difficult planar integration. In this paper, a novel and compact architecture of planar integrated dual-polarization quadrature mixer is proposed, focusing on the design of THz amplitude-phase balanced quadrature mixers. Based on anti-parallel Schottky diodes, a quadrature subharmonic mixer in the 330 GHz band has been designed. Measurement results show that, the single sideband conversion loss is 10.5-13.5 dB in the range of 310-348 GHz, and the image rejection ratio is basically better than 15 dB. The THz quadrature mixer proposed in this paper can be used as an optical fiber extender or THz wireless bridge to establish high-speed wireless links in areas where optical fibers are difficult or expensive to lay out.

关键词： Wireless communication Radio frequency Optical fiber polarization Multiplexing Schottky diodes Transceivers Optical fiber communication Loss measurement Mixers Terahertz communications

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A Fast Compact CMOS Feedforward Automatic Gain Control Circuit

A Fast Compact CMOS Feedforward Automatic Gain Control Circu...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.5

作者： J. P. Alegre B. Calvo S. Celma Electronic Design Group University of Zaragoza Zaragoza Spain

This paper presents a fast settling compact feedforward automatic gain control (AGC) suitable for use in wireless communication systems such as WLAN or Bluetooth receivers where the use of traditional closed loop feedback amplifiers forms a boundary due to the stringent settling time constraints. The AGC has been implemented in a 0.35 (mu)m standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 to 18 dB. The settling time of the circuit is below 0.25 (mu)s.

关键词： Gain control circuits CMOS technology Wireless communication Wireless LAN Bluetooth Feedback amplifiers Time factors Energy consumption Frequency

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A 24GHz Low-Power CMOS Receiver design

A 24GHz Low-Power CMOS Receiver Design

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.3

作者： Chen-Yuan Chu Chien-Cheng Wei Hui-Chen Hsu Shu-Hau Feng Wu-Shiung Feng Department of Electronic Engineering Chang Gung University Tao-Yuan Taiwan

A 24GHz low-power CMOS RF receivers for indoor wireless application is developed in this paper. This paper presents a novel approach to integrate the RF front-end circuits, and realizes the manufacture of SoC (System on a Chip) design. The proposed RF IC includes a low-noise amplifier (LNA), a down-conversion mixer, a voltage-controlled oscillator (VCO) and a variable gain amplifier (VGA). For the demands of a low-power design, the LNA and VCO were designed with current-reused technology for lowering the dc power consumption, and the current-bleeding approach was adopted in mixer design for boosting its conversion gain, respectively. The proposed 24GHz CMOS RF receiver achieves the overall conversion gain of 23.4dB with noise figure of 5.4dB, and the total power consumption is only 31.65mW. Compared to the other papers published over the past few years, this paper exhibits a better potential in low-power design than other receivers applied in the same frequency band.

关键词： Radio frequency Voltage-controlled oscillators Low-noise amplifiers Gain Energy consumption Integrated circuit manufacture Pulp manufacturing System-on-a-chip Radiofrequency integrated circuits Radiofrequency amplifiers

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Timing-Driven Obstacles-Avoiding Routing Tree Construction for A Multiple-layer System

Timing-Driven Obstacles-Avoiding Routing Tree Construction f...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.4

作者： Hsin-Hsiung Huang Hui-Yu Huang Yu-Cheng Lin Tsai-Ming Hsieh Department of Electronic Engineering Chung Yuan Christian University Chungli Taiwan Department of Information and Computer Engineering Chung Yuan Christian University Chungli Taiwan Department of Information and Electronic Commerce Kainan University Taoyuan Taiwan Department of Computer Science and Info. Engineering National Taitung University Taitung Taiwan

In this paper, we formulate the timing-driven multiple-layer obstacle-avoiding rectilinear Steiner minimal tree (TML-OARSMT) problem and propose an algorithm to solve the problem. The objective is simultaneously to minimize the maximum source-to-terminal length and minimize the number of vias. The proposed algorithm contains the three steps, including the multiple-level timing-driven partitioning, the multiple-level routing tree construction with obstacles, and the timing-driven multiple-layer balanced tree construction. Compared with the traditional method, the partition-based method can significantly improve the maximum source-to-terminal length and the total wirelength by 11.3percent and 10.9percent respectively with the additional number of vias.

关键词： Routing Delay Timing Partitioning algorithms Algorithm design and analysis Packaging Iterative algorithms Tree graphs electronic commerce Computer science

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The ALICE TPC front end electronics

The ALICE TPC front end electronics

引用

ieee symposium on Nuclear Science (NSS/MIC)

作者： L. Musa J. Baechler N. Bialas R. Bramm R. Campagnolo C. Engster F. Formenti U. Bonnes R. Esteve Bosch U. Frankenfeld P. Glassel C. Gonzales H.-A. Gustafsson A. Jimenez A. Junique J. Lien V. Lindenstruth B. Mota P. Braun-Munzinger H. Oeschler L. Osterman R. Renfordt G. Ruschmann D. Rohrich H.-R. Schmidt J. Stachel A.-K. Soltveit K. Ullaland CERN Geneva Switzerland Institute für Kemphysik Johann-Wolfgang-Universitat Frankfurt Germany Institut für Kernphysik Technische Universität Darmstadt Germany GSI Darmstadt Germany Physikalisches Institut Ruprecht-Karls-Universität Heidelberg Germany Division of High Energy Physics University of Lund Sweden University of Bergen Bergen Norway Kirchhoff_ Institut für Physik Ruprecht-Karls-Universität Heidelberg Germany

In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS). A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the system meets all design requirements. Originally conceived and optimized for the time projection chamber (TPC) of the ALICE experiment, its architecture and programmability make this system suitable for the readout of a wider class of detectors.

关键词： Control systems Application specific integrated circuits Detectors Data acquisition electronic equipment testing Tail Filters Cables Distributed control Prototypes

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Centroiding and Classification of Objects Using a Processor Array with a Scalable Region of Interest

Centroiding and Classification of Objects Using a Processor ...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.5

作者： Mika Laiho Jonne Poikonen Ari Paasio Kari Halonen Microelectronics Laboratory University of Turku Turku Finland Electronic Circuit Design Laboratory Helsinki University of Technology Finland

In this paper we describe how the location and size of an object in a multi-object scene can be identified and classified using a processor array with a scalable region of interest. Objects of interest can be classified by matching them with 25-pixel object prototypes in a window that is adjustable from 17X17 to 5X5. Matlab simulations of the algorithms are shown. In order to carry out the operations effectively, the processor is equipped with a global OR and global sum. Also, the outputs of the row and column decoders can be determined by boundary cell outputs, in addition to the address bits. A 64X64-cell array has been sent to fabrication.

关键词： circuits Layout Laboratories Image segmentation Iterative decoding Shape control Cameras Analog-digital conversion Image converters Logic programming

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Real-time imaging system using a 12-MHz forward-looking catheter with single chip CMUT-on-CMOS array

Real-time imaging system using a 12-MHz forward-looking cath...

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ieee symposium (IUS) Ultrasonics

作者： Coskun Tekes Toby Xu Thomas M. Carpenter Sebastian Bette Uwe Schnakenberg David Cowell Steven Freear Ozgur Kocaturk Robert J. Lederman F. Levent Degertekin George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA Institute of Materials in Electrical Engineering RWTH Aachen University Aachen Germany School of Electronic and Electrical Engineering University of Leeds Leeds United Kingdom Division of Intramural Research National Institute of Health Bethesda Maryland USA

ISBN: (纸本)9781479981830

Forward looking (FL) imaging catheters would be an important tool for several intravascular ultrasound (IVUS) and intracardiac echocardiography (ICE) applications. Single chip capacitive micromachined ultrasonic transducer (CMUT) arrays fabricated on front-end CMOS electronics with simplified electrical interconnect have been previously developed for highly flexible and compact catheters. In this study, we present a custom built real time imaging system utilizing catheters with single chip CMUT-on-CMOS arrays and show initial imaging results. The fabricated array has a dual-ring structure with 64 transmit (Tx) and 56 receive (Rx) elements. The CMUT arrays fit on a 2.1 mm diameter circular region with all the required front-end electronics. The device operates at 12 MHz center frequency and has around 20 V collapse voltage. The single-chip system requires 13 external connections including 4 Rx channels and power lines. The electrical connections to micro cables in the catheter are made from the top side of the chip using polyimide flex tapes. The device is placed on a 6-Fr catheter shaft and secured with a medical grade silicon rubber. For real time data acquisition, we developed a custom design FPGA based imaging platform to generate digital control sequences for the chip and collect RF data from Rx outputs. We performed imaging experiments using wire phantoms immersed in water to test the real time imaging system. The system has the potential to generate images at 32 fps rate with the particular catheter. The overall system is fully functional and shows promising image performance.

关键词： Catheters Imaging Arrays Flexible printed circuits Gold Real-time systems Polyimides

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PSRR of Bridge-Tied Load PWM Class D Amps

PSRR of Bridge-Tied Load PWM Class D Amps

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.1

作者： Tong Ge Joseph S. Chang Wei Shu School of Electrical and Electronic Engineering Nanyang Technological University Singapore

In this paper, the effects of power supply noise, qualified by Power Supply Rejection Ratio (PSRR), on two types of Bridge-Tied Load (BTL) Pulse Width Modulation (PWM) Class D Amps (denoted as Type-I BTL and Type-II BTL respectively) are investigated and the analytical expressions for PSRR of the two designs derived. The derived analytical expressions are verified by means of HSPICE simulations. The relationships derived herein provide good insight to the design of BTL Class D amps, including how various parameters may be varied/optimized to meet a given PSRR specification. Furthermore, the PSRR of the two BTL Class D amps are compared against the single-ended Class D amp, and the former designs show superior PSRR compared to the latter.

关键词： Pulse width modulation Power supplies Pulsed power supplies Digital modulation Signal to noise ratio Space vector pulse width modulation Feedback loop design engineering Power engineering and energy Analytical models

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design of a Networked Control System to Integrate Vehicular electronic Devices

Design of a Networked Control System to Integrate Vehicular ...

引用

2007 ieee International symposium on Industrial electronics (ISIE 2007), vol.7

作者： Miguel A. Dominguez Perfecto Marino Francisco Poza Santiago Otero Electronic Technology Department E.T.S.I: Industriales University of Vigo Spain

The electrical circuits and their electronic Control Units (ECUs) in buses and coaches are essential for their good working. Drive, braking, suspension, opening door, security and communication devices must be integrated in a reliable and real time information system. The industrial communication networks or fieldbuses are a good solution to implement networked control systems for the onboard electronics in the public transport buses and coaches. The authors are working in the design of multiplexed solutions based on fieldbuses to integrate the body and chassis functions of city public transport buses. An example for the EURO5 model of the Scania manufacturer is reported in this paper. The authors are also working in the implementation of new modules based on FPGAs (Field Programmable Gate Arrays) that can be used in these networked control systems.

关键词： Networked control systems Vehicular and wireless technologies Field programmable gate arrays Communication system control Communication system security Information security Integrated circuit reliability Telecommunication network reliability Real time systems Information systems

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10GBase-LX4 Optical Fiber Receiver in a 0.18(mu)m Digital CMOS Process

10GBase-LX4 Optical Fiber Receiver in a 0.18(mu)m Digital CM...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.7

作者： J. M. Garcia del Pozo M. T. Sanz S. Celma A. Otin J. P. Alegre J. Sabadell Group of Electronic Design University of Zaragoza Zaragoza Spain Centro Nacional de Microelectrónica Barcelona Spain

In this paper, a monolithic CMOS optical receiver designed in a 0.18(mu)m digital process suitable for 10GBase-LX4 optical fiber transmissions is described. The system is based on CMOS actively loaded inverter structures and works with a single 1.8 V supply voltage. The thermal effects are minimized between -20 and 80 deg C by using two different compensation techniques. The design presents optimized area and power consumption.

关键词： Optical fibers Optical receivers CMOS process Energy consumption Costs Optical amplifiers Optical design Voltage CMOS technology Bandwidth

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