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A 1-V CMOS Front-End for High-Speed 1-mm SI-POF Links

A 1-V CMOS Front-End for High-Speed 1-mm SI-POF Links

引用

ieee Latin American symposium on circuits and systems

作者： C. Gimeno C. Aldea S. Celma F. Aznar Group of Electronic Design - Aragon Institute of Engineering Research (GDE-I3A) University of Zaragoza

ISBN: (纸本)9781467312073

This paper presents a new CMOS analog front end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm SI-POF transmission systems and is suitable for the required large area Si PIN photodetector. The prototype contains a transimpedance amplifier, a continuous-time equalizer, and an output driver. In particular, the proposed front end has been designed using a cost-effective digital 0.18μm CMOS technology and is fed with only 1 V, targeting gigabit transmission for simple NRZ modulation. Simulation results validate the approach for cost-effective gigabit SI-POF transmission.

关键词： front-ends analog front end output driver Transmission systems Complementary Metal Oxide Semiconductor transimpedance amplifier nonreturn to zero transimpedance

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PERFORMANCE EVALUATION OF DCT AND WAVELET TRANSFORM FOR LSI

PERFORMANCE EVALUATION OF DCT AND WAVELET TRANSFORM FOR LSI

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.8

作者： Tareq Jaber Abbes Amira Peter Milligan School of Electronics Electrical Engineering and Computer Science Queen''s University Belfast Belfast UK Electronic and Computer Engineering School of Engineering and Design Brunel University of West London Uxbridge Middlesex UK

Latent semantic indexing (LSI) is commonly used to match queries to documents in information retrieval (IR) applications. This paper presents a new philosophy for LSI, investigating the use of various hybrid approaches and presents a novel evaluation strategy based on the use of image processing tools. The authors evaluate the use of the discrete cosine transform (DCT) and Cohen Daubechies Feauveau 9/7 (CDF9/7) wavelet transform as a pre-processing step for the singular value decomposition (SVD) step of the LSI system. In addition, the effect of different threshold types on the search results is examined. The results show that accuracy can be increased by applying both transforms as a pre-processing step, with better performance for the hard-threshold function. The choice of the best threshold value is a key factor in the transform process.

关键词： Discrete cosine transforms Wavelet transforms Large scale integration Image databases Discrete wavelet transforms Image processing Time division multiplexing design engineering Indexing Information retrieval

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Optimization of design Parameters Using Taguchi Method for Thermal Stress Analysis in a 3D IC

Optimization of Design Parameters Using Taguchi Method for T...

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International Conference on Computer Applications and Industrial electronics (ICCAIE)

作者： Syamil Bin Sazali Hasliza Binti Hassan Norliana Yusof Yusnira Husaini Anees Binti Abdul Aziz Tuan Norjihan Binti Tuan Yaakub School of Electrical Engineering College of Engineering Universiti Teknologi MARA (UiTM) Shah Alam Selangor Fakulti Teknologi Kejuruteraan Universiti Tun Hussein Onn Malaysia (UTHM)) Panchor Johor Fakulti Reka Bentuk Inovatif dan Teknologi Universiti Sultan Zainal Abidin (UniSZA) Terenganu Integrated Microelectronic System and Applications (IMSaA) School of Electrical Engineering College of Engineering Universiti Teknologi MARA (UiTM) Shah Alam Selangor

ISBN: (数字)9798350348798

ISBN: (纸本)9798350348804

Thermal stress and deformation analysis plays an important role in understanding the effects of heat on the performance and reliability of a 3D integrated circuit (IC) design. The demand for smaller and powerful electronic devices, 3D IC design gained prominence due to their superior integration capabilities. The IC's components dissipate heat across several chip regions, which may cause localized overheating and a decline in performance and reliability. Hence, there is a growing need for innovative solutions to address this issue. The main objective of this project is to develop a 3D IC thermal model using Ansys Software. The study also aims to optimize the design parameters to predict the hot spots region in the 3D IC. The size of the intermetallic compound (IMC) joint, chip thickness, and load temperature were chosen as factors to evaluate the effect of various variables on the thermal stress of the 3D IC. The findings suggest that the temperature loading has a substantial impact on the thermal stress experienced by the 3D IC model. The IMC joint and chip interface were identified as the critical locations where higher thermal stress were perceived. Upon optimizing the variables, the thermal stress and deformation experienced a reduction of 1.25% and 0.36% respectively. In summary, the most effective design parameters for this study were determined to be a chip size of 0.9 mm, an IMC joint size of 0.1 mm, and a chip thickness of 0.12 mm. These parameters were obtained under the temperature load of 60 °C.

关键词： Integrated circuits Heating systems Solid modeling Three-dimensional displays electronic packaging thermal management Thermal analysis Thermal loading

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Advancing the State-of-the-Art in Hardware Trojans design

Advancing the State-of-the-Art in Hardware Trojans Design

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ieee Pulsed Power Conference

作者： Syed Kamran Haider Chenglu Jin Marten van Dijk Department of Electrical and Computer Engineering University of Connecticut

ISBN: (纸本)9781509063901

electronic design Automation (EDA) industry heavily reuses third party IP cores which are vulnerable to insertion of Hardware Trojans (HTs) at design time by third party IP core providers. State of the art research has shown that existing HT detection techniques, which claim to detect all publicly available HT benchmarks, can still be defeated by carefully designing new sophisticated HTs. The reason being that these techniques consider the HT landscape to be limited only to the publicly known HT benchmarks. However the adversary is not limited to these HTs and may devise new HT design principles to bypass these countermeasures. In this paper, we discover certain crucial properties of trigger activated HTs which lead to the definition of an exponentially large class of Deterministic Hardware Trojans H_D that an adversary can (but is not limited to) design. The discovered properties serve as HT design principles which help us understand the tremendous ways available to an adversary to design a HT, and show that the existing publicly known HT benchmarks are just the tip of the iceberg on this huge landscape.

关键词： Computer hardware Arts BENCHMARKS design year electronic design automation design theory icebergs Third party high-temperature superconductors EIS IMPLEMENTATION PLANS state of the art Vulnerable terminal interface processor

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Blind Identification of MIMO Channels with Periodic Precoders

Blind Identification of MIMO Channels with Periodic Precoder...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.1

作者： Weizhou Su Qingqi Bi Wei Xing Zheng Shengli Xie School of Automation Science and Engineering South China University of Technology Guangzhou China School of Computing and Mathematics University of Western Ontario NSW Australia School of Electronic and Information Engineering South China University of Technology Guangzhou China

This paper studies the blind identification problem for multiple-input multiple-output (MIMO) FIR channels, in which the source signals are modulated by high order periodic precoders. A set of new design criteria of the periodic precoders is proposed from the channel blind identification viewpoint for multiuser channels. It is shown that, due to the fact that high order periodic precoders are used in the modelling problem, certain simple orthogonality among user's signals can be introduced by a set of proper designed periodic precoders. This results in a simple blind identification algorithm and the impulse response of every subchannel can also be determined uniquely up to a unitary scalar based on the received signals' second order statistics (SOS) and a priori information of the periodic precoders. Simulation results illustrate that the developed blind identification algorithm is efficient.

关键词： Blind identification MIMO channels periodic precoders power spectral density function

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designs for multi-port bifurcated waveguide power dividers at millimeter-wave frequencies

Designs for multi-port bifurcated waveguide power dividers a...

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USNC-URSI Radio Science Meeting (Joint with AP-S symposium)

作者： Wei-Shiun Lan Dow-Chih Niu Eric S. Li Department of Electronic Engineering National Taipei University of Technology Taipei Taiwan 106 R.O.C. Chung-Shan Institute of Science and Technology Longtan Taiwan 303 R.O.C.

Su/mmary form only given. Power dividers have been extensively used in many microwave circuits and sub-systems such as feeding networks for antenna arrays and power amplifiers. For applications requiring high power-handling capability and low insertion loss, conventional E- and H-plane waveguide T-junctions would be the simplest three-port designs. However, due to their lossless nature and reciprocal property, such junctions cannot be matched simultaneously at all ports. In addition, poor isolation exists between their output ports. These problems place severe limitation on their practical applications. Bifurcated waveguide power dividers were proposed to solve the aforementioned problems. The early bifurcation design features a thin metallic plate inside a rectangular waveguide. The plate is positioned perpendicular to the TE 10 electric field, which is known as an E-plane bifurcation and is able to effectively convert the guide into two reduced-height waveguides. This design offers a solution to determine the power ratio of two output ports by taking the quotient of the two reduced heights of the bifurcated waveguide, but still fails to improve the isolation between the output ports. The introduction of a resistive coupling slot in the thin metallic plate was presented to solve the isolation problem (F. Takeda, O. Ishida, and Y. Isoda, ieee MTT-S Digest, 1982.) The resistive coupling slot consists of a transverse slot and a small resistor. The isolation between two output ports was increased up to at least 30 dB within a 10% frequency range of interest. For millimeter-wave applications, implementation of such resistive coupling slot presents difficulty if the cost and ease of fabrication need to be considered. Therefore, a resistive film was proposed to replace the thin metallic plate with a resistive coupling slot. Current resistive films are made of tantalum nitride (TaN) and must stay on a supportive object. They are usually available in two resistive values,

关键词： Films

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Mitigating Radiation Effects on ICs at Device and Architectural Levels: the SpaceWire Router Case Study

Mitigating Radiation Effects on ICs at Device and Architectu...

引用

2007 ieee International symposium on Industrial electronics (ISIE 2007), vol.8

作者： Esa Petri Sergio Saponara Marco Tonarelli Iacopo Del Corona Luca Fanucci Pierangelo Terreni Consorzio Pisa Ricerche - Applicazioni Microelettroniche (CPR-TEAM) Pisa Italy Dept. Information Engineering University of Pisa Pisa Italy

The mitigation of radiation effects on integrated circuits is discussed in this paper with reference to the design of hardware macrocells for reliable high-speed networking based on the SpaceWire standard. Target applications include on-board distributed control systems for aerospace, military, avionics or automotive scenarios. Due to CMOS technology scaling, digital ICs are becoming more susceptible to radiation effects, both Total Ionization Dose and Single Event Effects. This traditional issue of space and military systems is becoming a concern also for terrestrial electronic systems such as commercial avionics, high-radiation industrial environments and safety-critical automotive control systems. To optimize the trade-off between increased radiation-robustness and extra IC costs in terms of area, power consumption and weight, we present several ad-hoc design solutions both at device and architectural levels. As a result a single-device SpaceWire Router with 8 links and data-rates up to 100 Mbits/s is achieved featuring a TID of 300 krad and immunity to upset up to a Linear Energy Transfer threshold greater than 60 MeV mg/cm{sup}2.

关键词： Radiation effects Aerospace electronics Military standards Aerospace industry Automotive engineering CMOS technology Space technology Application specific integrated circuits High speed integrated circuits Hardware

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An Improved Method of Power Control with CMOS Class-E Power Amplifiers

An Improved Method of Power Control with CMOS Class-E Power ...

引用

2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.7

作者： Tongqiang Gao Chun Zhang Baoyong Chi Zhihua Wang Department of Electronic Engineering Tsinghua University Beijing China Institute of Microelectronics Tsinghua University Beijing China

In this paper, an improved method of power control is introduced to widen the range of output power with high efficiency. Two CMOS class-E power amplifiers (PA) with different output power are adopted in the design. In order to eliminate the phase mismatch of two paths, a continuously adjustable CMOS phase shifter with a predictable phase transfer function is added before each PA. Meanwhile, the drain modulation technique is presented to vary the voltage supply of the amplification unit. With the combination of drain modulation and parallel amplification, a wider range of output power is obtained than the previous one. The amplifiers work in 915MHz with the supply voltage of 1.8V and 2.5V. Simulation results show that the amplification unit could reach a maximum output power of 26dBm and maintain a power-added efficiency (PAE) higher than 40percent over the 18dBm-26dBm output power range.

关键词： Power control Power amplifiers Power generation Voltage Pulse amplifiers High power amplifiers Phase shifters Radiofrequency amplifiers Pulse modulation Power transmission lines

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Virtual Ground Fence Options for Shielding Power Plane Noise

Virtual Ground Fence Options for Shielding Power Plane Noise

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ieee International symposium on Electromagnetic Compatibility

作者： A. Ege Engin Jesse Bowman Department of Electrical and Computer Engineering San Diego State University 5500 Campanile Drive San Diego CA 92182-1309 U.S.A.

ISBN: (纸本)9781479955466

This paper demonstrates possible design approaches for the virtual ground fence, a novel design concept for shielding power plane noise. The basic idea of a virtual ground fence is replacing discrete capacitors with quarter-wave stubs. This allows decoupling of power plane noise in the GHz spectrum. Such noise filtering is critical in a mixed-signal system, where there is switching noise generated by the digital VLSI. This noise easily propagates to the sensitive RF IC if not filtered. The virtual ground fence consists of quarter-wave transmission-line stubs that act as short circuits at their design frequency. An array of such stubs can then be considered as a ground fence. Hence the power plane of the RF IC is effectively placed inside a Faraday cage, and isolated from the noise in the environment. Controlling noise enables designing faster and smaller electronic systems.

关键词： Radio frequency integrated circuits Noise fencing FARADAY CUPS quarter-wave design concept Common Channel Signaling noise environment ground design frequency Virtual plane Platanus hybrida Planing noise filtering

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Efficient scheduling of path delay tests for latch-based circuits

Efficient scheduling of path delay tests for latch-based cir...

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ieee VLSI Test symposium (VTS)

作者： Kun Young Chung Sandeep K. Gupta System LSI Division Samsung Electronics Co. Ltd. Electrical Engineering - Systems University of Southern California

ISBN: (纸本)9781424437696

In many high-speed parts of chips, latch-based circuits are used to enable time borrowing, where a block may take longer time than its nominal delay to complete its computation. This enables such circuits to attain high performance and yield. In [1] and [2], we focused on maximizing path delay fault coverage and proposed the first structural delay testing approach and the associated design-for-testability (DFT) for such circuits. This approach provides dramatically higher coverage of path delay faults. In this paper, we focus on minimizing test application cost for delay testing latch-based circuits while ensuring that maximum coverage is achieved. We show that conventional test scheduling methods may not be applicable due to the unique characteristics of latch-based circuits with time borrowing. We then formulate the minimization problem and propose two heuristic approaches. The experimental results show that, for many example circuits, the proposed approaches achieve overall test application costs that are within 5% of the corresponding lower-bounds.

关键词： Circuit testing Latches Costs electronic equipment testing Circuit faults Delay effects Clocks Logic testing System testing Robustness

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