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Measurements of power and current components in unbalanced and distorted three‐phase systems

European Transactions on Electrical Power 1993年第1期3卷 75-83页

作者： Andria, G. Salvatore, L. Savino, M. Trotta, A. Dr. Gregorio Andria (1956) AEI received the M. S. degree in Electrical Engineering from the State University of Bari/Italy in 1981 and the Ph. D. degree in Electrical Engineering in 1987 from the same University. From 1981 to 1983 he was working in the Electrotechnics and Electronics Department of the University of Bari as a member of the research team on electrical measurements. From 1984 to 1986 he was a Doctoral Fellow and currently he is a researcher in the same department. His research interests are in the fields of electrical and electronic measurements on components and systems including digital measurements for the analysis of electrical quantities in non-sinusoidal systems and the design of integrated optical sensors for measurement and control of non-electrical physical quantities. (Department of Electrotechnics and Electronics Faculty of Engineering polytechnic of Bovia E. Orabona 4 1-70125 Bari. Italy T +3980/242266 Fax + 3980/242410) Prof. Luigi Salvatore (1945) AEI received the degree in electrical engineering from the University of Bari/Italy in 1970. Since 1976 he has worked in the Electrotechnical and Electronic Department of the same University as a member of the research team on electrical machines. From 1983 to 1987 he was a researcher of electrical machines in the same department. Since 1987 he has been an Associate Professor of electrical machines at the University of Bari. At the present time his research interests include the control monitoring and diagnostics of AC drives and the areas of signal processing anddigital measurements on power electronics systems. (Department of Electrotechnics and Electronics Faculty of Engineering Polytechnic of Bari via E. Orabona 4 I-70125 Bari Italy T + 3980/242258 Fax + 3980/242410) Prof. Mario Savino (1947) AEI received the degree in Electrical Engineering from the University of Barif Italy in 1971. Since then he has been working in the Electrotechnical Institute of Bari until 1973 as researcher from 1973 to 1982 as Assistant Profe

The paper deals with the instantaneous power theory in three‐phase circuits by using the instantaneous time phasors of voltage and current. Particularly it is shown that the instantaneous components of the current time‐phasor in a rotating reference frame p‐q, oriented in such a way that the instantaneous voltage time‐phasor points to the p‐axis direction, represent the active and reactive currents. These components give rise to instantaneous real and imaginary powers, respectively. The spectral analysis of the above‐mentioned time‐phasors gives the harmonic symmetrical components of positive and negative sequence of voltage and current three‐phase systems. The line‐by‐line product of the voltage sequence spectrum by the complex conjugate of the current sequence spectrum gives the DC components of the instantaneous real and imaginary powers. The paper shows also that the instantaneous active and reactive currents are different from those defined on grounds of the Fryze's theory, which can be determined from the voltage and current sequence spectra. Copyright © 1993 John Wiley & Sons, Ltd.

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Simulation of Switching circuits using Transfer Functions

Simulation of Switching Circuits using Transfer Functions

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ieee Pulsed Power Conference

作者： David Kebo Houngninou Mitchell A. Thornton Department of Computer Science and Engineering SMU Darwin Deason Institute for Cyber Security SMU

ISBN: (纸本)9781509063901

Simulation of complex hardware circuits is the basis for many EDA tasks and is commonly used at various phases of the design flow. State-of-the-art simulation tools are based upon discrete event simulation algorithms and are highly optimized and mature. Symbolic simulation may also be implemented using a discrete event approach, or other approaches based on extracted functional models. The common foundation behind modern simulation tools is that of a switching or Boolean algebraic model that may be augmented with timing information. Recently, an alternative foundational model for conventional digital electronic circuits has been proposed, based upon linear algebra rather than Boolean switching algebra where the circuits are modeled as transfer functions in the form of linear transformation matrices. We demonstrate that this model can be effectively used as the basis for a simulation methodology. Our approach is motivated by the need to develop a truly unified EDA tool for mixed signal circuit design. Currently, industrial tools such as SPECTRE use two different internal engines;a SPICE-like engine and a Verilog-like engine. Our method will allow us to represent mixed signal circuit elements as transfer functions. Spatial complexity is significantly reduced through the use of binary decision diagrams (BDD) to represent the transfer functions. A prototype implementation is used to generate experimental results and to illustrate the viability of the linear algebraic model as a basis for EDA applications.

关键词： Switching Circuit Simulation Symbolic Simulation Transfer Function Binary Decision Diagram

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A Novel Optimization Framework for the design of Gilbert Cell Mixers

A Novel Optimization Framework for the Design of Gilbert Cel...

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ieee Pulsed Power Conference

作者： G. Piccinni G. Avitabile G. Coviello C. Talarico Electronic and Information Engineering Department Polytechnic of Bari Department of Electrical and Computer Engineering Gonzaga University

ISBN: (纸本)9781509063901

This paper presents a new framework for the design optimization of a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The framework exploits the g_m/I_D methodology to find the transistors' dimensions that optimize the tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the mixer. The mixer has been designed using a 0.13 μm process from IHP Microelectronics, and it exhibits a conversion gain of 13.1 dB at 0 dBm local oscillator's power. The average noise figure is 11.9 dB, the input third-order intercept is -2.8 dBm and the output third-order intercept is 9.7 dBm. Finally, the chip-core without bonding pads measures only 0.028 mm by 0.031 mm and it dissipates 1.5 mW with a 1.5 V supply.

关键词： Double balanced mixer Down-conversion mixer Gilbert cell G_m over I_D

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Multilayer Graphene Nanoribbon Based BioFET Sensor design

Multilayer Graphene Nanoribbon Based BioFET Sensor Design

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ieee Pulsed Power Conference

作者： Nahid M. Hossain Emeshaw Ashenafi Moqbull Hossen Azzedin Es-Sakhi Masud H. Chowdhury Computer Science and Electrical Engineering University of Missouri - Kansas City

ISBN: (纸本)9781509063901

High performance biofunctionalized field effect transistors (BioFETs) use nanoscale electronic materials such as silicon nanowires (SiNWs), carbon nanotubes (CNT) and graphene for the sensing application. Specific focus will be on high-performance, low-cost, scalable, and reliable biofunctionalized field effect transistor (BioFET) based on graphene. We attempted to build the graphene based sensing device on silicon substrate. We are proposing a biosensor where graphene could be used as a channel material and extended gate for ion detection. The idea is to combine existing concepts of biosensors based on ion-sensitive field-effect transistor (ISFET) and chemically modified field-effect transistors (CHEMFET), and implement it on a new Graphene nanoribbons (GNR) based BioFET. Both ISFET and CHEMFET concepts are based on floating-gate transistor operation similar to that of Flash memory design. In this paper, we will explore regular transistor based graphene FET (GFET) intended for biosensing application.

关键词： Biosensor GNR GFET CHEMFET ISFET

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Characterizing fast-scale instability in a buck-based switching amplifier for wideband tracking

Characterizing fast-scale instability in a buck-based switch...

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2008 ieee International symposium on circuits and systems (ISCAS 2008), vol.10

作者： E. Rodriguez F. Guinjoan A. Poveda E. Alarcon A. El-Aroudi Department of Electronic Engineering Technical University Catalunya Barcelona Spain Department of Electronics and Automatics Universitat Rovira i Virgili Tarragona Spain

This paper provides a first exploration of fast-scale stability borders for switching power converters operating as wideband switching amplifiers. Such operation is required in audio amplifiers, envelope trackers in polar RF transmitters and line drivers for Power Line Communications. A buck converter with output voltage proportional feedback in a signal tracking configuration with a sinusoidal reference is considered (Figure 1). The work first characterizes the effect of the classical set of parameters used in regulation stability analysis (output resistance, reactive components, switching frequency, feedback gain), and considers the output voltage to cover the complete dynamic range and hence disappear as a variable in the parametric space. Complementarily, the effect of the ratio of the tracking or baseband frequency to the switching frequency is added as a new variable in the design space indicative of wideband tracking operation. Characterization tools encompass families of time domain simulations as dynamic bifurcation diagrams for the time-varying reference. The paper concludes by exploring the effect of momentarily losing fast-scale stability upon the output signal spectrum, since applications such as adaptive supply of RF power amplifier are subject to strict spectral masks.

关键词： Broadband amplifiers Radiofrequency amplifiers Communication switching Power amplifiers Stability Radio frequency Voltage Output feedback Switching frequency Switching converters

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How SI/EMC and reliability issues could interact together in embedded electronic systems?

How SI/EMC and reliability issues could interact together in...

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ieee International symposium on Electromagnetic Compatibility

作者： Kirsten Weide-Zaage Aymen Moujbani Genevieve Duchamp Tristan Dubois Frederic Verdier Helene Fremont RESRI Group Institute of Microelectronic Systems (IMS-AS) Leibniz Universitat Hannover Hannover Germany Universite de Bordeaux IMS Bordeaux - CNRS UMR 5218 Talence France

ISBN: (纸本)9781479966172

The design process of integrated circuits is based on guidelines by the technological feasibility to achieve minimum structural size. Furthermore quality criteria like reliability and lifetime of the circuit influence the layout. The density of transistors increases and the supplied voltages as well as the noise margins also increase. In this frame the signal integrity as well as the electromagnetic behavior of IC interconnects, the traces in the printed circuit board, the connections of packages, have to be taken into account. Especially in 3-D integration and under harsh environment conditions the electromagnetic field has to be investigated.

关键词： simulation electromigration signal integrity reliability

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A 0.5V fully differential transimpedance amplifier in 65-nm CMOS technology

A 0.5V fully differential transimpedance amplifier in 65-nm ...

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ieee Pulsed Power Conference

作者： Hugo Garcia-Vazquez Fortunato Carlos Dualibe Grigory Popov Analog and Mixed Signal Design Group Electronic and Microelectronic Unit University of Mons

ISBN: (纸本)9781509063901

This paper proposes a novel fully differential ultra-low voltage transimpedance amplifier (TIA) based on a CMOS translinear circuit. Following a simple bias strategy, its transimpedance gain can be adjusted to the desired accuracy either by means of an external resistor or using internal voltage and current references. To a first order approach, the transresistance results independent from technological parameters. The amplifier does not need a common mode feedback circuit (CMFB) to set the quiescent output voltages. The circuit was sized and simulated in a 65-nm CMOS process to comply with a 10kΩ transimpedance gain and 1MHz@1pF bandwidth. For a 0.5V supply voltage the total power consumption is 78.5μW.

关键词： Transimpedance Amplifier Fully differential CMOS 65-nm RF front end Mixer IoT

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designing Elementary-Tree Space Compressors Using AND/NAND and XOR/XNOR Combinations

Designing Elementary-Tree Space Compressors Using AND/NAND a...

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ieee International Instrumentation and Measurement Technology Conference

作者： Nicholas A. Malan Sunil R. Das Satyendra N. Biswas Mansour H. Assaf Scott Morton Emil M. Petriu Voicu Groza Department of Computer Science College of Arts and Sciences Troy University Montgomery AL 36103 USA Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology Dhaka 1208 Bangladesh Department of Electrical and Electronic Engineering University of the South Pacific (USP) Suva 19128 Fiji School of Information Technology and Engineering Faculty of Engineering University of Ottawa Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9781479961153

Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of very large scale integration circuits and systems is of great significance, especially in view of the technological paradigm shift in recent years from system-on-board to system-on-chip design. This paper investigates and provides new approach to realizing aliasing-free elementary-tree space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test, the paper introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND and XOR/XNOR logic. The process is illustrated in the paper with details of synthesis of space compressors for the International symposium on circuits and systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using fault simulation programs ATALANTA, FSIM and HOPE, exemplifying the relevance of the technique from the standpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, making it thus a logical choice in commercial design environments.

关键词： Built-in self-testing in very large scale integration cores-based system-on-chips fault detection compatibility and conditionalfault detection compatibility space compression

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Data Compression Using Mixed Cascade of Nonlinear Logic

Data Compression Using Mixed Cascade of Nonlinear Logic

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ieee International Instrumentation and Measurement Technology Conference

作者： Sunil R. Das Danny L. Shaw Satyendra N. Biswas Mansour H. Assaf Scott Morton Irem Ozkarahan Emil M. Petriu Voicu Groza Department of Computer Science College of Arts and Sciences Troy University Montgomery AL 36103 USA School of Engineering and Computer Science Independent University Dhaka 1329 Bangladesh Department of Electrical and Electronic Engineering University of the South Pacific Suva Fiji School of Information Technology and Engineering Faculty of Engineering University of Ottawa Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9781467346214

The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zero-aliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other pair of response data outputs being simultaneously fault detection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International symposium on circuits and systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.

关键词： Aliasing-free (zero-aliasing) space compaction ATALANTA built-in self-testing in very large scale integration circuits and systems fault detection and conditional fault detection compatibility

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