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A Concept Towards Pressure-Controlled Microfluidic Networks 25

A Concept Towards Pressure-Controlled Microfluidic Networks

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25th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Fink, Gerold Hamidovic, Medina Haselmayr, Werner Wille, Robert Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria Johannes Kepler Univ Linz Inst Commun Engn & RF Syst Linz Austria Tech Univ Munich Chair Design Automat Munich Germany Software Competence Ctr Hagenberg GmbH SCCH Hagenberg Austria

ISBN: (纸本)9781665494311

Droplet-based microfluidic networks interconnect multiple microfluidic modules which allow to process (e.g., mix, sort, heat, incubate) so-called payload droplets (i.e., droplets containing a biological sample) on a single microfluidic chip. Inside such networks the path of a droplet and, thus, the module which processes it, can be controlled by microfluidic switches. Thus far, these switches are realized by injecting additional control droplets into the network which allow to trigger the switching mechanism by solely exploiting passive hydrodynamic effects. While this eliminates the need of expensive components such as valves, this droplet-controlled switching concept is very sensitive and already slight deviations, e.g., in the control droplet injection could lead to incorrectly triggered switches. In this work, we address this issue by proposing a new concept of pressure-controlled networks which omit the control droplets (and their drawbacks) and, instead, use a single pump in order to drive the switches. Using design automation expertise together with established models, we derive a corresponding blueprint which realizes this idea for a specific network architecture. Simulations based on established methods and design tools confirmed the suitability of the proposed pressure-controlled networks.

关键词： Process control Switches Network architecture Control systems Valves Hydrodynamics design tools

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design of an ECG front-end considering ST segment distortion 14

Design of an ECG front-end considering ST segment distortion

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14th ieee Latin American symposium on circuits and systems (LASCAS)

作者： Guenego, Beatrice Lelandais-Perrault, Caroline Avignon-Meseldzija, Emilie Sou, Gerard Benabes, Philippe Univ Paris Saclay Lab Genie Elect & Elect Paris GeePs Cent Supelec CNRS Gif Sur Yvette France

ISBN: (纸本)9781665457057

ECG ST segment should be monitored for myocardial ischemia diagnosis. But this information needs a very accurate ECG acquisition. This paper presents the design of a chopper amplifier filtering the baseline wander and minimizing the added electronic noise with an acceptable ST segment distortion. A method is proposed to estimate the ST segment distortion and compare it to the International Electrotechnical Commission (IEC) standards. The design is achieved using XFAB 180nm technology and validated at transistor-level simulation for typical and worst cases.

关键词： Electrocardiogram (ECG) Chopper Amplifier Myocardial Ischemia Signal Distortion ST segment Embedded baseline wander elimination

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Knowledge transfer. From electronic design Automation to Advanced Process Manufacturing 67

Knowledge transfer. From Electronic Design Automation to Adv...

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67th ieee International Midwest symposium on circuits and systems (MWSCAS)

作者： Torres, J. Andres Tao, Melody Doinychko, Anastasiia Govindaraj, Mohan Jayaram, Srividya Greeneltch, Nathan Siemens Digital Ind Wilsonville OR 97070 USA Siemens Digital Ind Fremont CA USA Siemens Digital Ind Grenoble France

ISBN: (纸本)9798350387186;9798350387179

On the path towards more complex systems that deliver more value at lower cost in semiconductor products, the industry had to develop frameworks to support the rapid design of very complex systems giving rise to widespread adoption of VLSI. A very similar situation exists for the advanced manufacturing process supporting the semiconductor industry. In order to keep the pace of innovation in manufacturing technology, the concept of a Digital Twin has been the main target of multiple studies and proposals. In this work we demonstrate that by learning from the lessons of VLSI, we aim to construct a digital twin of the manufacturing process that permits the monitoring and optimization of the most important aspects of semiconductor manufacturing, while at the same time demonstrating that such agnostic approach can also be applied to other manufacturing operations. A key component to the digital twin is the creation and deployment of reliable, experimentally verified machine learning models. In this work we will present necessary model characteristics to meet such requirements, under data conditions that are atypical for traditional machine learning training methods.

关键词： VLSI SOC Semiconductor Manufacturing Machine Learning Digital Twin Knowledge Transfer Feature Engineering

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A Trim-free PVT Invariant Current Reference with 0.48% process inaccuracy using VTH Tracking Approach 67

A Trim-free PVT Invariant Current Reference with 0.48% proce...

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67th ieee International Midwest symposium on circuits and systems (MWSCAS)

作者： Kuncham, Vishnu Gopal, Jalluri Ram Pradhith, V. S. S. Atmakuri, Aniketh Mittal, Chetan Le, Khanh M. Abbas, Zia Int Inst Informat Technol Hyderabad India Analog Intelligent Design Inc Santa Clara CA USA

ISBN: (纸本)9798350387186;9798350387179

The prevalence of MOSFETs in diverse electronic applications highlights their significance. However, the sensitivity of MOSFET threshold voltage to process variation poses a substantial challenge in achieving consistent device performance. This paper proposes a novel approach to overcome this challenge by employing a threshold voltage (V-TH) tracking circuit that tracks the variation in V-TH. Our primary objective is to develop a current reference that remains invariant across process, voltage, and temperature (PVT) variations, eliminating the need for an external trimming circuit. This is achieved by the meticulous integration of V-TH tracking circuit, CTAT generator, PTAT generator, and a current adder. By employing this design, a process variation (sigma/mu) of 0.48%, a temperature coefficient (TC) of 210ppm/degrees C for a temperature range of -40 degrees C to 120 degrees C, and a line sensitivity of 1.6% is achieved over a voltage range of 1.6V - 3V. The proposed circuit occupies an area of 0.013mm(2) while consuming power of 56 mu W at a typical corner of 27 degrees C and a supply of 1.8V. The given circuit is implemented in a 180nm CMOS process node with a generated reference current of 61nA.

关键词： PVT invariant proportional to absolute temperature (PTAT) complementary to absolute temperature (CTAT) V-TH tracking circuit beta-multiplier

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Quality-driven design Methodology for PUFs in FPGAs for Secure IoT 24

Quality-driven Design Methodology for PUFs in FPGAs for Secu...

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24th International symposium on Quality electronic design (ISQED)

作者： Wang, Xiangyun Song, Yicheng Prakash, Katyayani Zilic, Zeljko Langsetmo, Tomas McGill Univ Montreal PQ Canada KNOX Ind Inc Montreal PQ Canada

ISBN: (纸本)9798350334753

The emergence of Internet of Things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since Field-Programmable Gate Arrays (FPGAs) are more trusted than custom Integrated circuits (ICs) in building secure systems, implementing PUFs in FPGAs is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on FPGAs. With our method, an asymmetric delay-based PUF has been predictably designed for temperature- and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.

关键词： Physical Unclonable Function (PUF) Internet-of-Things (IoT) Field-Programmable Gate Array (FPGA) Hardware Security design Methodology

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Proceedings - 37th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design, SBCCI 2024

Proceedings - 37th SBC/SBMicro/IEEE/ACM Symposium on Integra...

引用

37th SBC/SBMicro/ieee/ACM symposium on Integrated circuits and systems design, SBCCI 2024

ISBN: (纸本)9798350391695

The proceedings contain 39 papers. The topics discussed include: design of low-power 5.8-GHz ULV LNTAs using normalized biasing metric;design of low-power 5.8-GHz ULV LNTAs using normalized biasing metric;voltage coefficient of resistance effect in the harmonic distortion of active-RC continuous-time sigma-delta modulators;EAVREF: an evolutionary algorithm based tool for low-power CMOS voltage reference designs;a nanomagnetic logic based processor;NoX: a compact open-source RISC-V processor for multi-processor systems-on-chip;investigating the influence of process variability on asymmetric multicore processors;an evolutionary search for energy recovery opportunities in partially reversible FCN circuits;robustness analysis of atomic silicon quantum dot logic gates;and enhancing manycore lifetime through reinforcement learning task mapping and migration.

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Ka-band Tx Integrated circuits in 0.13 μm SiGe BiCMOS for AESA for SATCOM Applications 15

Ka-band Tx Integrated Circuits in 0.13 μm SiGe BiCMOS for A...

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15th Latin American symposium on circuits and systems (LASCAS)

作者： Sette, Elmo Lintignat, Julien Lohou, Anael Barelaud, Bruno Jarry, Bernard Univ Limoges CNRS UMR 7252 XLIM Limoges France SAFRAN DATA Syst La Teste De Buch France

ISBN: (纸本)9798350381221;9798350381238

This paper proposes the design of an active Vector Modulator (VM) and a Variable Gain Power Amplifier (VGPA) for an active electronic scanning antenna (AESA) in Ka-band (Tx). The VM is composed of three main blocks: a balun, a second-order polyphase filter (I/Q network), and Variable Gain Amplifiers (VGA). The VGPA is a two-stage amplifier: control and power. The circuit designs are presented using 130 nm BiCMOS9MW technology from ST Microelectronics (R). For the VM, simulations show good phase results around 30 GHz. Insertion losses are less than -6 dB across the entire band and regardless of phase state. Consumption is less than 115 mW. For the VGPA, simulations show saturated output power greater than 16.5 dBm, power gain greater than 20 dB with Power-Added Efficiency (PAE) greater than 20 %. Dynamic gain and 1-dB output compression point (OCP1dB) are greater than 12 dB and 15 dBm respectively. The circuits have an area of 2.6 mm(2) and 1.26 mm(2) respectively.

关键词： active phase shifters AESA gain control Kaband SATCOM variable gain amplifiers vector modulator

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New perspective on understanding contact between metal and oxide through atomistic modeling: a case study on tin oxide in contact with common metals

New perspective on understanding contact between metal and o...

引用

ieee International symposium on the Physical and Failure Analysis of Integrated circuits (IPFA)

作者： Tian, Yujia Kripalani, Devesh Xue, Ming Gan, Swee Lee Zhou, Kun Nanyang Technol Univ Sch Mech & Aerosp Engn 50 Nanyang Ave Singapore 639798 Singapore Intineon Technol Asia Pacific Pte Ltd 168 Kallang Way Singapore 349282 Singapore

ISBN: (纸本)9798350360615;9798350360608

Remarkable efforts have been devoted to the detection, location, and resolution of electrical contact failures. However, because of the complex interplay of physical, mechanical, and electrical factors as well as the continuous miniaturization of electronic devices to the nanoscale, current methods that rely on conventional contact resistance measurements face significant limitations. By adopting the approach of atomistic modeling, our study tackles this persistent issue by providing a new perspective on fundamentals of contact mechanisms. As an example, the contact between common metals and tin oxide is systematically evaluated and compared by examining the charge transfer and bonding at the interface. The obtained theoretical results serve as the principles for explaining the contact behavior of such materials systems and provide more insights and practical guidance on materials selection, troubleshooting and problem solving, as well as device design.

关键词： metal-semiconductor contact electronic properties Schottky barrier metal-induced gap states atomistic modeling first-principles calculations two-dimensional materials

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Live Demonstration: Pitanga Platform for Virtual FPGA Remote Laboratories 56

Live Demonstration: Pitanga Platform for Virtual FPGA Remote...

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56th ieee International symposium on circuits and systems (ISCAS)

作者： Costa, Alcides S. Silveira, Leonardo D. Reis, Andre I. Univ Fed Rio Grande do Sul Inst Informat PPGC Porto Alegre RS Brazil Univ Fed Rio Grande do Sul Inst Informat PGMICRO Porto Alegre RS Brazil inPlace Design Automat Ivoti RS Brazil

ISBN: (纸本)9781665451093

This paper introduces the Pitanga platform and its potential as an alternative for FPGA remote laboratories. The platform consists of a virtual electronic board and a built-in virtual programmable logic device. The interface is innovative in that it utilizes a remote FPGA emulator running on standard x86 processors rather than a physical FPGA board. This software-based approach makes the platform more reliable, scalable, and accessible to low-budget institutions that may not have the resources to acquire traditional FPGA-based educational boards. Our live demonstration at ISCAS 2023 showcases the equivalence of experiments on the Pitanga platform and physical FPGA boards from a user's perspective, making it a viable option as a complement or alternative to traditional FPGA remote labs for digital circuit experimentation.

关键词： Digital circuit design Remote laboratory VLSI Education FPGA Emulation Programmable logic

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Feasible All-Optical OR and NOR Logic Gates in Photonic Crystals 16

Feasible All-Optical OR and NOR Logic Gates in Photonic Crys...

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16th ieee Latin American symposium on circuits and systems, LASCAS 2025

作者： Novy, Gabriel Felipe Candido Alves, Julio Cesar Teodoro Ramirez, Jhonattan Cordoba Neto, Omar Paranaiba Vilela Belo Horizonte Brazil Belo Horizonte Brazil Belo Horizonte Brazil

ISBN: (纸本)9798331522124

This work presents the design and simulation of photonic crystal-based OR and NOR logic gates, aimed at eliminating the need for dynamic control signals dependent on input combinations. Utilizing silicon-based photonic crystals operating at a 1550 nm wavelength, the gates exhibit enhanced performance, making them suitable for optical computing. Simulation results confirm the reliability of the proposed designs, with the OR and NOR gates achieving contrast ratios of 5.3 dB and 5.1 dB, respectively. Innovative waveguide junctions play a crucial role in minimizing signal loss and preserving signal integrity. This work advances photonic computing by offering a simplified control mechanism while maintaining high performance, paving the way for more energy-efficient and faster alternatives to traditional electronic logic gates. Future research directions include experimental validation and integration into more complex photonic circuits. © 2025 ieee.

关键词： Logic design

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